Simulation Results: aes

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.39 %
  • code
  • 95.49 %
  • assert
  • 98.21 %
  • func
  • 80.48 %
  • block
  • 95.97 %
  • line
  • 97.27 %
  • branch
  • 91.14 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
91.43%
V2S
95.24%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 71.748us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 74.506us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 123.622us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 76.197us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 238.039us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 206.945us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 72.906us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 76.197us 1 1 100.00
aes_csr_aliasing 2.000s 206.945us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 74.506us 1 1 100.00
aes_config_error 3.000s 189.203us 1 1 100.00
aes_stress 8.000s 869.060us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 74.506us 1 1 100.00
aes_config_error 3.000s 189.203us 1 1 100.00
aes_stress 8.000s 869.060us 1 1 100.00
back2back 2 2 100.00
aes_stress 8.000s 869.060us 1 1 100.00
aes_b2b 16.000s 802.583us 1 1 100.00
backpressure 1 1 100.00
aes_stress 8.000s 869.060us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 74.506us 1 1 100.00
aes_config_error 3.000s 189.203us 1 1 100.00
aes_stress 8.000s 869.060us 1 1 100.00
aes_alert_reset 2.000s 43.431us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 67.605us 1 1 100.00
aes_config_error 3.000s 189.203us 1 1 100.00
aes_alert_reset 2.000s 43.431us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 6.000s 679.431us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 702.151us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 2.000s 43.431us 0 1 0.00
stress 1 1 100.00
aes_stress 8.000s 869.060us 1 1 100.00
sideload 2 2 100.00
aes_stress 8.000s 869.060us 1 1 100.00
aes_sideload 2.000s 67.594us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 154.023us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 40.000s 4306.583us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 61.407us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 298.680us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 298.680us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 123.622us 1 1 100.00
aes_csr_rw 2.000s 76.197us 1 1 100.00
aes_csr_aliasing 2.000s 206.945us 1 1 100.00
aes_same_csr_outstanding 2.000s 105.146us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 123.622us 1 1 100.00
aes_csr_rw 2.000s 76.197us 1 1 100.00
aes_csr_aliasing 2.000s 206.945us 1 1 100.00
aes_same_csr_outstanding 2.000s 105.146us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 110.302us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 122.592us 1 1 100.00
aes_control_fi 2.000s 62.381us 1 1 100.00
aes_cipher_fi 2.000s 47.586us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 123.807us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 123.807us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 123.807us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 123.807us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 162.885us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 409.453us 1 1 100.00
aes_tl_intg_err 3.000s 490.093us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 490.093us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 2.000s 43.431us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 123.807us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 74.506us 1 1 100.00
aes_stress 8.000s 869.060us 1 1 100.00
aes_alert_reset 2.000s 43.431us 0 1 0.00
aes_core_fi 2.000s 71.032us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 123.807us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 60.711us 1 1 100.00
aes_stress 8.000s 869.060us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 8.000s 869.060us 1 1 100.00
aes_sideload 2.000s 67.594us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 60.711us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 60.711us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 60.711us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 60.711us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 60.711us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 8.000s 869.060us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 8.000s 869.060us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 122.592us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 122.592us 1 1 100.00
aes_control_fi 2.000s 62.381us 1 1 100.00
aes_cipher_fi 2.000s 47.586us 1 1 100.00
aes_ctr_fi 2.000s 50.851us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 122.592us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 122.592us 1 1 100.00
aes_control_fi 2.000s 62.381us 1 1 100.00
aes_cipher_fi 2.000s 47.586us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 47.586us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 122.592us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 122.592us 1 1 100.00
aes_control_fi 2.000s 62.381us 1 1 100.00
aes_ctr_fi 2.000s 50.851us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 122.592us 1 1 100.00
aes_control_fi 2.000s 62.381us 1 1 100.00
aes_cipher_fi 2.000s 47.586us 1 1 100.00
aes_ctr_fi 2.000s 50.851us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 2.000s 43.431us 0 1 0.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 122.592us 1 1 100.00
aes_control_fi 2.000s 62.381us 1 1 100.00
aes_cipher_fi 2.000s 47.586us 1 1 100.00
aes_ctr_fi 2.000s 50.851us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 122.592us 1 1 100.00
aes_control_fi 2.000s 62.381us 1 1 100.00
aes_cipher_fi 2.000s 47.586us 1 1 100.00
aes_ctr_fi 2.000s 50.851us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 122.592us 1 1 100.00
aes_control_fi 2.000s 62.381us 1 1 100.00
aes_ctr_fi 2.000s 50.851us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 122.592us 1 1 100.00
aes_control_fi 2.000s 62.381us 1 1 100.00
aes_cipher_fi 2.000s 47.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 3.000s 246.126us 0 1 0.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS)
aes_alert_reset 67705873953304070085348542969292664361068023356519315439979190172013614700061 1483
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 43431451 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 43331451 PS)
UVM_ERROR @ 43431451 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_INFO @ 43431451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 86359799677220288606999737912427814729761765556550698490346012343989187337220 177
UVM_FATAL @ 246126078 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 246126078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---