Simulation Results: chip

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.77 %
  • code
  • 85.18 %
  • assert
  • 96.44 %
  • func
  • 39.69 %
  • line
  • 94.33 %
  • branch
  • 93.66 %
  • cond
  • 89.33 %
  • toggle
  • 91.42 %
  • FSM
  • 57.14 %
Validation stages
V1
95.65%
V2
87.99%
V2S
100.00%
V3
66.67%
unmapped
62.50%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 96.680s 2161.371us 1 1 100.00
chip_sw_example_rom 75.010s 3157.121us 1 1 100.00
chip_sw_example_manufacturer 122.670s 3050.996us 1 1 100.00
chip_sw_example_concurrency 144.640s 3275.011us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 199.730s 7887.038us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 341.480s 5501.035us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 1848.640s 31000.874us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4706.390s 36524.015us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 44.580s 2531.947us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4706.390s 36524.015us 1 1 100.00
chip_csr_rw 341.480s 5501.035us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.080s 230.581us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 276.820s 3965.487us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 276.820s 3965.487us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 276.820s 3965.487us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 332.880s 3866.357us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 332.880s 3866.357us 1 1 100.00
chip_sw_uart_tx_rx_idx1 314.600s 4309.974us 1 1 100.00
chip_sw_uart_tx_rx_idx2 359.190s 4525.788us 1 1 100.00
chip_sw_uart_tx_rx_idx3 350.740s 3764.766us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 277.020s 3916.012us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 392.930s 4519.774us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 220.360s 3842.343us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 208.870s 5502.564us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 208.870s 5502.564us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 182.250s 3669.440us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 164.140s 5473.037us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 139.800s 2706.737us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 89.980s 2851.798us 1 1 100.00
chip_tap_straps_testunlock0 301.220s 5556.732us 1 1 100.00
chip_tap_straps_rma 95.090s 2538.231us 1 1 100.00
chip_tap_straps_prod 440.300s 7767.678us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 97.980s 2883.304us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 687.440s 8469.873us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 363.120s 5340.700us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 363.120s 5340.700us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 488.130s 6526.050us 1 1 100.00
chip_sw_ast_clk_rst_inputs 1 1 100.00
chip_sw_ast_clk_rst_inputs 2418.100s 25644.700us 1 1 100.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 309.830s 3510.893us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 535.760s 6091.272us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3196.800s 18402.383us 1 1 100.00
chip_sw_aes_enc_jitter_en 139.720s 2666.578us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 622.810s 7207.167us 1 1 100.00
chip_sw_hmac_enc_jitter_en 139.530s 2406.277us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 637.050s 7232.607us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 210.820s 3328.348us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 313.820s 4106.251us 1 1 100.00
chip_sw_clkmgr_jitter 85.360s 2045.074us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 209.460s 3220.405us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 360.400s 4883.265us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 249.860s 5106.909us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 133.490s 2461.774us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 249.860s 5106.909us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 105.680s 2502.979us 1 1 100.00
chip_sw_aes_smoketest 169.440s 2749.782us 1 1 100.00
chip_sw_aon_timer_smoketest 139.310s 2151.192us 1 1 100.00
chip_sw_clkmgr_smoketest 138.780s 2946.745us 1 1 100.00
chip_sw_csrng_smoketest 128.010s 2723.655us 1 1 100.00
chip_sw_entropy_src_smoketest 851.020s 7724.445us 1 1 100.00
chip_sw_gpio_smoketest 164.770s 3112.379us 1 1 100.00
chip_sw_hmac_smoketest 226.530s 3406.643us 1 1 100.00
chip_sw_kmac_smoketest 197.520s 2996.933us 1 1 100.00
chip_sw_otbn_smoketest 1329.350s 11203.255us 1 1 100.00
chip_sw_pwrmgr_smoketest 230.400s 6057.101us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 245.350s 4836.049us 1 1 100.00
chip_sw_rv_plic_smoketest 152.720s 2478.355us 1 1 100.00
chip_sw_rv_timer_smoketest 122.750s 2451.909us 1 1 100.00
chip_sw_rstmgr_smoketest 119.700s 2637.249us 1 1 100.00
chip_sw_sram_ctrl_smoketest 91.020s 2525.878us 1 1 100.00
chip_sw_uart_smoketest 145.990s 2439.523us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 145.310s 2522.992us 1 1 100.00
chip_sw_rom_functests 1 1 100.00
rom_keymgr_functest 283.920s 4050.501us 1 1 100.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7779.560s 61968.882us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2390.040s 14418.488us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 706.470s 15087.552us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 212.360s 3278.942us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 136.830s 2905.916us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6851.260s 54037.121us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 6734.860s 57242.856us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 45.920s 2534.353us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 45.920s 2534.353us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4706.390s 36524.015us 1 1 100.00
chip_same_csr_outstanding 1116.760s 14852.729us 1 1 100.00
chip_csr_hw_reset 199.730s 7887.038us 1 1 100.00
chip_csr_rw 341.480s 5501.035us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4706.390s 36524.015us 1 1 100.00
chip_same_csr_outstanding 1116.760s 14852.729us 1 1 100.00
chip_csr_hw_reset 199.730s 7887.038us 1 1 100.00
chip_csr_rw 341.480s 5501.035us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 29.400s 564.787us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.640s 46.605us 1 1 100.00
xbar_smoke_large_delays 38.330s 6203.106us 1 1 100.00
xbar_smoke_slow_rsp 62.500s 6341.297us 1 1 100.00
xbar_random_zero_delays 35.490s 583.702us 1 1 100.00
xbar_random_large_delays 86.510s 15231.411us 1 1 100.00
xbar_random_slow_rsp 91.850s 10856.205us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 20.160s 294.430us 1 1 100.00
xbar_error_and_unmapped_addr 9.800s 309.855us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 11.490s 443.853us 1 1 100.00
xbar_error_and_unmapped_addr 9.800s 309.855us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 57.630s 2291.294us 1 1 100.00
xbar_access_same_device_slow_rsp 462.250s 54226.205us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 18.580s 1002.820us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 36.250s 751.465us 1 1 100.00
xbar_stress_all_with_error 100.950s 2291.307us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 145.070s 576.277us 1 1 100.00
xbar_stress_all_with_reset_error 40.190s 297.938us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2390.040s 14418.488us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2481.190s 36497.858us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2379.980s 15542.196us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2013.130s 11600.415us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2598.790s 16780.722us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2596.050s 17400.492us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2600.880s 17178.503us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2473.620s 15757.245us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 23.760s 10.320us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 16.820s 10.380us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 17.670s 10.280us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 17.670s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 22.420s 10.220us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 19.040s 10.360us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 18.840s 10.380us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 16.580s 10.180us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 16.630s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 15.800s 10.140us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.360s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 16.360s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.840s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 16.450s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.940s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.000s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 18.640s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 18.560s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 16.390s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 17.210s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.210s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.630s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.430s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 16.830s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18.070s 10.240us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2003.500s 11168.537us 1 1 100.00
rom_e2e_asm_init_dev 2508.490s 16746.083us 1 1 100.00
rom_e2e_asm_init_prod 2462.910s 15859.452us 1 1 100.00
rom_e2e_asm_init_prod_end 2439.390s 15916.253us 1 1 100.00
rom_e2e_asm_init_rma 2298.800s 15178.635us 1 1 100.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 2305.700s 16778.529us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 4157.000s 31016.516us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 4102.210s 28726.056us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2478.710s 17107.256us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2896.810s 34619.948us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2896.810s 34619.948us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 148.410s 2551.157us 1 1 100.00
chip_sw_aes_enc_jitter_en 139.720s 2666.578us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 126.120s 2788.101us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 116.810s 2598.936us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1082.120s 10677.580us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 191.330s 2651.369us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 287.850s 5432.962us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 381.920s 5354.140us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 463.330s 5747.264us 1 1 100.00
chip_plic_all_irqs_10 261.130s 3616.923us 1 1 100.00
chip_plic_all_irqs_20 331.720s 3983.311us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 186.260s 3949.409us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1117.090s 13300.739us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 327.210s 5372.629us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 132.080s 3185.404us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 884.180s 6889.016us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 694.140s 6281.238us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 847.210s 7823.752us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8330.580s 255422.480us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 229.220s 3448.174us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 230.400s 6057.101us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 229.220s 3448.174us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 364.500s 6938.638us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 364.500s 6938.638us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 219.210s 6510.654us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 259.770s 4117.337us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 543.240s 5459.335us 1 1 100.00
chip_sw_aes_idle 116.810s 2598.936us 1 1 100.00
chip_sw_hmac_enc_idle 134.750s 3405.505us 1 1 100.00
chip_sw_kmac_idle 93.650s 2087.960us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 169.810s 3874.989us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 289.010s 4538.682us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 288.410s 4680.545us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 240.530s 4549.626us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 913.150s 11728.732us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 397.900s 4077.777us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 345.640s 4966.551us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 307.780s 4134.965us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 343.630s 4549.727us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 355.840s 4015.244us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 337.230s 4492.288us 1 1 100.00
chip_sw_ast_clk_outputs 488.130s 6526.050us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 577.820s 9892.508us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 307.780s 4134.965us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 343.630s 4549.727us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 309.830s 3510.893us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 535.760s 6091.272us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3196.800s 18402.383us 1 1 100.00
chip_sw_aes_enc_jitter_en 139.720s 2666.578us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 622.810s 7207.167us 1 1 100.00
chip_sw_hmac_enc_jitter_en 139.530s 2406.277us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 637.050s 7232.607us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 210.820s 3328.348us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 313.820s 4106.251us 1 1 100.00
chip_sw_clkmgr_jitter 85.360s 2045.074us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 138.290s 2468.808us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 376.250s 4586.737us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 626.470s 7053.705us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 2984.170s 24591.814us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 110.960s 2271.652us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 137.390s 2712.562us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1169.710s 12665.384us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 152.310s 3093.978us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 326.160s 4469.858us 1 1 100.00
chip_sw_flash_init_reduced_freq 1068.090s 23194.396us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 13628.810s 172246.190us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 488.130s 6526.050us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 334.820s 4982.659us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 244.250s 3346.198us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 381.920s 5354.140us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 884.180s 6889.016us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1023.540s 7647.913us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 286.520s 4417.273us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 384.760s 5847.930us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 145.310s 2889.296us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3253.460s 20276.102us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 131.600s 3064.139us 1 1 100.00
chip_sw_edn_entropy_reqs 629.760s 7109.162us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 131.600s 3064.139us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1023.540s 7647.913us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 127.280s 2873.318us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1029.520s 17360.767us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 528.520s 5018.590us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 535.760s 6091.272us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 350.500s 4003.034us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 309.830s 3510.893us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3398.410s 44436.757us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1029.520s 17360.767us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 198.320s 3446.281us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1067.830s 9536.667us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 293.170s 5354.078us 1 1 100.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3398.410s 44436.757us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 293.170s 5354.078us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 293.170s 5354.078us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_wr_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 293.170s 5354.078us 1 1 100.00
chip_sw_flash_lc_seed_hw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 293.170s 5354.078us 1 1 100.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 381.920s 5354.140us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 90.160s 4384.962us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 502.990s 5323.727us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 314.630s 5372.575us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 314.630s 5372.575us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 177.800s 3017.436us 1 1 100.00
chip_sw_hmac_enc_jitter_en 139.530s 2406.277us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 134.750s 3405.505us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 595.670s 6140.567us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 704.150s 6209.988us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 450.060s 5406.391us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 312.320s 4310.640us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 427.310s 5245.535us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 261.020s 3837.735us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1067.830s 9536.667us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 637.050s 7232.607us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1642.730s 12556.660us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1082.120s 10677.580us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2739.540s 15826.519us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 146.420s 3028.353us 1 1 100.00
chip_sw_kmac_mode_kmac 159.000s 2774.799us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 210.820s 3328.348us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1067.830s 9536.667us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 479.190s 10148.398us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 157.700s 2756.410us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1348.130s 9831.522us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 93.650s 2087.960us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 287.850s 5432.962us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 89.980s 2851.798us 1 1 100.00
chip_tap_straps_rma 95.090s 2538.231us 1 1 100.00
chip_tap_straps_prod 440.300s 7767.678us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 121.310s 2125.949us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 479.190s 10148.398us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 479.190s 10148.398us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 479.190s 10148.398us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1208.810s 8622.461us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_prim_tl_access 90.160s 4384.962us 1 1 100.00
chip_rv_dm_lc_disabled 138.020s 6423.138us 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 293.170s 5354.078us 1 1 100.00
chip_sw_flash_rma_unlocked 3398.410s 44436.757us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 169.970s 3402.774us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 527.540s 5530.565us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 478.290s 7166.944us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 356.370s 4896.394us 0 1 0.00
chip_sw_lc_ctrl_transition 479.190s 10148.398us 1 1 100.00
chip_sw_keymgr_key_derivation 1067.830s 9536.667us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 336.120s 9221.827us 1 1 100.00
chip_sw_sram_ctrl_execution_main 382.430s 6993.429us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 577.820s 9892.508us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 397.900s 4077.777us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 345.640s 4966.551us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 307.780s 4134.965us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 343.630s 4549.727us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 355.840s 4015.244us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 337.230s 4492.288us 1 1 100.00
chip_tap_straps_dev 89.980s 2851.798us 1 1 100.00
chip_tap_straps_rma 95.090s 2538.231us 1 1 100.00
chip_tap_straps_prod 440.300s 7767.678us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 114.670s 3742.538us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 87.720s 3124.226us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 97.970s 3221.142us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 155.680s 3741.265us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_rv_dm_lc_disabled 138.020s 6423.138us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1546.280s 28024.779us 1 1 100.00
chip_sw_lc_walkthrough 5 5 100.00
chip_sw_lc_walkthrough_dev 3719.130s 49566.753us 1 1 100.00
chip_sw_lc_walkthrough_prod 4093.690s 50723.247us 1 1 100.00
chip_sw_lc_walkthrough_prodend 502.620s 10242.175us 1 1 100.00
chip_sw_lc_walkthrough_rma 3837.860s 47514.791us 1 1 100.00
chip_sw_lc_walkthrough_testunlocks 1546.280s 28024.779us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 61.980s 2811.746us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 71.800s 3150.025us 1 1 100.00
rom_volatile_raw_unlock 75.230s 2920.565us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3238.450s 16528.123us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3196.800s 18402.383us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 543.240s 5459.335us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 543.240s 5459.335us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 543.240s 5459.335us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 289.240s 3325.300us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 479.190s 10148.398us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1029.520s 17360.767us 1 1 100.00
chip_sw_otbn_mem_scramble 289.240s 3325.300us 1 1 100.00
chip_sw_keymgr_key_derivation 1067.830s 9536.667us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 264.200s 4231.048us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 126.220s 2778.180us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1029.520s 17360.767us 1 1 100.00
chip_sw_otbn_mem_scramble 289.240s 3325.300us 1 1 100.00
chip_sw_keymgr_key_derivation 1067.830s 9536.667us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 264.200s 4231.048us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 126.220s 2778.180us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 479.190s 10148.398us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 278.530s 4833.561us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 121.310s 2125.949us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 90.160s 4384.962us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 169.970s 3402.774us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 527.540s 5530.565us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 478.290s 7166.944us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 356.370s 4896.394us 0 1 0.00
chip_sw_lc_ctrl_transition 479.190s 10148.398us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 90.160s 4384.962us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 678.230s 6722.684us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 285.560s 5976.022us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1301.330s 24166.744us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 193.910s 6715.776us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 281.780s 6744.462us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 266.540s 6953.581us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 905.670s 22341.012us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 2 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 581.490s 12476.315us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 364.500s 6938.638us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 763.270s 10529.577us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 240.780s 4899.545us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 285.560s 5976.022us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 151.850s 3405.111us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 348.520s 10589.634us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 265.110s 7854.295us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 300.980s 4290.908us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1132.370s 20488.421us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 506.850s 7447.942us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 881.130s 10320.833us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1309.800s 20700.217us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 170.260s 3121.590us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 381.920s 5354.140us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 336.120s 9221.827us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 336.120s 9221.827us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 881.130s 10320.833us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1132.370s 20488.421us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 240.780s 4899.545us 1 1 100.00
chip_sw_pwrmgr_smoketest 230.400s 6057.101us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 232.230s 4579.150us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 309.250s 5343.910us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 267.690s 5046.406us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1117.090s 13300.739us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 115.230s 3213.220us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 381.920s 5354.140us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 694.140s 6281.238us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 484.700s 4547.190us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 456.470s 4955.935us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 186.610s 3109.753us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 126.220s 2778.180us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 309.250s 5343.910us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 309.250s 5343.910us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 191.960s 4155.233us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 901.400s 13110.011us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 232.230s 4579.150us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 173.460s 3195.734us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 193.150s 6155.593us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 95.090s 2538.231us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 138.020s 6423.138us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 463.330s 5747.264us 1 1 100.00
chip_plic_all_irqs_10 261.130s 3616.923us 1 1 100.00
chip_plic_all_irqs_20 331.720s 3983.311us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 106.710s 2749.678us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 170.630s 3374.545us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2390.040s 14418.488us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 438.940s 6917.071us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 140.010s 2493.735us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 174.350s 3621.506us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 167.700s 2963.211us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 264.200s 4231.048us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 313.820s 4106.251us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 330.100s 6195.634us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 308.550s 8987.824us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 382.430s 6993.429us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 381.920s 5354.140us 1 1 100.00
chip_sw_data_integrity_escalation 363.120s 5340.700us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 506.850s 7447.942us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1048.240s 22135.889us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 143.350s 2499.684us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 224.680s 3421.368us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 268.360s 4220.415us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1048.240s 22135.889us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1048.240s 22135.889us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2305.160s 20472.029us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2305.160s 20472.029us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 238.210s 5838.406us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2896.810s 34619.948us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 105.560s 2617.672us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 166.070s 3562.675us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 256.310s 4002.429us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 297.630s 4288.338us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1003.330s 7616.739us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4823.100s 31160.871us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1759.980s 11701.812us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 157.680s 2827.660us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 144.870s 2845.803us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 94.860s 2594.650us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 8959.570s 72367.305us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1053.370s 6110.809us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 426.580s 14835.887us 0 1 0.00
rom_e2e_jtag_debug_dev 355.970s 5434.262us 0 1 0.00
rom_e2e_jtag_debug_rma 147.070s 3546.712us 0 1 0.00
rom_e2e_jtag_inject 1 3 33.33
rom_e2e_jtag_inject_test_unlocked0 255.210s 5721.327us 1 1 100.00
rom_e2e_jtag_inject_dev 82.020s 2900.883us 0 1 0.00
rom_e2e_jtag_inject_rma 93.220s 2743.234us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 9.208s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 1 1 100.00
chip_sw_clkmgr_jitter_frequency 501.720s 4610.711us 1 1 100.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 296.570s 3311.196us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 617.320s 4449.848us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1041.320s 7861.670us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 224.490s 2384.208us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 541.470s 5221.377us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 120.170s 2447.554us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 204.450s 3088.649us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 225.380s 5833.687us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 203.590s 3935.836us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 881.130s 10320.833us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 426.580s 14835.887us 0 1 0.00
rom_e2e_jtag_debug_dev 355.970s 5434.262us 0 1 0.00
rom_e2e_jtag_debug_rma 147.070s 3546.712us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 244.620s 4878.240us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 381.920s 5354.140us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5270.190s 38386.298us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5270.190s 38386.298us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 167.200s 3683.286us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 332.880s 3866.357us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3190.470s 18602.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 5 8 62.50
chip_sival_flash_info_access 142.590s 2981.759us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 287.840s 4712.130us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 70.490s 2289.812us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 116.970s 3179.223us 1 1 100.00
chip_sw_otp_ctrl_descrambling 142.190s 2819.467us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 234.750s 3732.296us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 13.270s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 210.770s 3564.116us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32623) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 77464908693133070175320400129401404071967911210786054474172291213213248271266 214
UVM_ERROR @ 2534.353112 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32623) { a_addr: 'h107b0 a_data: 'hc5ca9ab2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h18 a_opcode: 'h4 a_user: 'h1957a d_param: 'h0 d_source: 'h18 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2534.353112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 39536313340042721945535113951568611173696625469568479764444760641491544233879 242
UVM_ERROR @ 6423.137906 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x106a8 read out mismatch
UVM_INFO @ 6423.137906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31575) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 102851023240549900386047036036804606319977739156171685301360656621978573464550 221
UVM_ERROR @ 2531.947280 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31575) { a_addr: 'h1036c a_data: 'hff0a8a21 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3 a_opcode: 'h4 a_user: 'h1a2e0 d_param: 'h0 d_source: 'h3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2531.947280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 70042573965340966988175921597659364637470100009859811367734177621310879204463 419
UVM_ERROR @ 2493.734987 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 2493.734987 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 29987465750208906578888515668814962625298054074196446949952584319447090664350 432
UVM_ERROR @ 4896.393597 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 4896.393597 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 75951128766533274683337077485930198614109635887095045155701606428206206530524 407
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3088.648752 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3088.648752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
chip_sw_otp_ctrl_rot_auth_config 92049721808094729525236633768766400952198610608231954304173614292804066085004 426
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 81880130261150921195654877521048222526264209195819572088416273627061864302183 419
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 19328774615229445735166556891733515967734626231179232166265090953274012003228 453
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 26150573592698055411083865876316138790606932431368997250077579710919774028493 422
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 52736791078141541194010424964151744681900237116377152118979529783354624746770 419
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 41228782715617190068802163398651049713920637045876768219997721314232772300420 419
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@111781) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 22920808736601656820263807784616438814680002079810884336407853225680349577797 413
UVM_ERROR @ 5343.909590 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@111781) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 5343.909590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_por_reset 90446212372948779420379111173592072328408631477342549139421831163944359790091 417
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 6744.462000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6744.462000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 77746764114393055935128462128718609303669823002275801578075673854873294525987 412
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 10589.634000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10589.634000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 46708429012024650354871478838642151566394406458876583270167549728191072722094 414
UVM_ERROR @ 34619.947916 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34619.947916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 54981543930908310824552102886401159346167650985675392685350547014592926645589 390
UVM_ERROR @ 2651.369074 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
UVM_INFO @ 2651.369074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 2054789263454686944350918999197169749009987499363825112968696035133382786133 390
UVM_ERROR @ 3185.404040 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3185.404040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 50183979746246993692199305404442004266508735150616927026940316835262331603721 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 111174845173445714681112259324855364065028820366308114876393421365843303883451 406
UVM_ERROR @ 3732.296490 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
UVM_INFO @ 3732.296490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 100765870534989854128263749134563347012804844553220159990485697852844354409836 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.747s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 838904650023576108990846810538609676612226513678426717509769368243965023432 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.161s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 102208635365526887288349273060405631924234342998576188269646840671840085574587 393
UVM_ERROR @ 3278.942000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3278.942000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 8789996798962470561597584438632515880410344007243623275979302874730984538353 403
UVM_ERROR @ 2905.915500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 2905.915500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 92847740708580092473062934590487753041123714358757920630576675977174988124315 472
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 115390219809300636128877042095937834922195505604387333712380665813304566541000 477
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 6476356311240482282323836738826268438524812977706441713895854526391302156875 496
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 66373468182079917185309527892395280676082394084833505354087088706703737411260 489
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 62049547563868376334940681064015622356803291397876185515648033633168956585505 497
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 79244283125406033366747048285693920366629218680216276516671804983248303668261 472
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 96061211492665445260099424888417361212439080242952258816081992238420799471448 489
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 80198333593569967846379047730559194508921669759530870745055900769186777438085 498
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 23536893604146495920412397895041431712626177615684722429820968526331352624783 509
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 80174245971078294523397660658506089185927252621311260612416136695175299788195 517
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 35159918528547378392293501119475962614405848935358736264857349150789374938439 583
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 14726217917648540073328236659262563631789441671596150748144514152479624192167 566
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 95062123923989626887237349985497377636763543157075741388472238696291615048594 595
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 95384752880563076037845972160006680995481473255032839384911682598091261499697 500
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 66541738457547960091780169821237125145971392871435709671768620773336349595641 519
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 6805244955813062919512072613459276652066127157120500966208317840884817161017 471
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 19022251570233925600696870458798103095528258291328983827638137990941659128054 591
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 96521671771023003932594298029370202933232322394946938836898095567957198717720 487
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 7490712882252617765480684511455370418437043562994174156046679544799345003716 556
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 100895836098240381968842368779617964268984532272773010052506506177508571254968 513
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 52673155093756452859466377064803774092583810594415307373948799620313703278165 494
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 102003724996511813275289204695853704743187827402895694377973900185385884549680 518
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 25796927445230352014556636974898031439553774545521231747512341738296688397269 497
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 25961167875408827818416368364786483733809426356568570748976116495876813797989 498
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3838263329131545228188768539224942362090032268062282214030772856635150335185 515
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
rom_e2e_jtag_debug_test_unlocked0 94246091938963967903743124959226397356687229496684509956427504796140016149345 432
UVM_FATAL @ 14835.887053 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 14835.887053 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 43388053502829775063417834098504310589327481125989166369290873108240934655134 417
UVM_ERROR @ 16778.528771 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16778.528771 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
rom_raw_unlock 65873103888261566954547775837150527863933598068355443147614047398037782422831 436
UVM_FATAL @ 15087.552195 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
UVM_INFO @ 15087.552195 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---