Simulation Results: csrng

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.85 %
  • code
  • 92.55 %
  • assert
  • 93.23 %
  • func
  • 80.77 %
  • block
  • 97.31 %
  • line
  • 97.87 %
  • branch
  • 93.25 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 24.838us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 26.610us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 15.920us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 4.000s 64.866us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 81.158us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 43.729us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 15.920us 1 1 100.00
csrng_csr_aliasing 4.000s 81.158us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
alerts 1 1 100.00
csrng_alert 10.000s 776.575us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 142.000s 14980.676us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 142.000s 14980.676us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 8.000s 443.995us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 46.411us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 39.400us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 28.452us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 28.452us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 26.610us 1 1 100.00
csrng_csr_rw 2.000s 15.920us 1 1 100.00
csrng_csr_aliasing 4.000s 81.158us 1 1 100.00
csrng_same_csr_outstanding 2.000s 17.498us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 26.610us 1 1 100.00
csrng_csr_rw 2.000s 15.920us 1 1 100.00
csrng_csr_aliasing 4.000s 81.158us 1 1 100.00
csrng_same_csr_outstanding 2.000s 17.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 3.000s 48.797us 1 1 100.00
csrng_sec_cm 4.000s 230.893us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 2.000s 15.920us 1 1 100.00
csrng_regwen 2.000s 12.394us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 10.000s 776.575us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 8.000s 443.995us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
csrng_sec_cm 4.000s 230.893us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
csrng_sec_cm 4.000s 230.893us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
csrng_sec_cm 4.000s 230.893us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
csrng_sec_cm 4.000s 230.893us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
csrng_sec_cm 4.000s 230.893us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 10.000s 776.575us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 8.000s 443.995us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 10.000s 776.575us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 48.797us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
csrng_sec_cm 4.000s 230.893us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
csrng_sec_cm 4.000s 230.893us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 155.003us 1 1 100.00
csrng_err 3.000s 31.854us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
csrng_stress_all_with_rand_reset 160.000s 4598.425us 1 1 100.00

Error Messages

   Test seed line log context