Simulation Results: flash_ctrl

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.59 %
  • code
  • 94.06 %
  • assert
  • 96.62 %
  • func
  • 96.10 %
  • line
  • 95.92 %
  • branch
  • 97.15 %
  • cond
  • 93.96 %
  • toggle
  • 98.24 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.73%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 32.020s 132.141us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.660s 31.831us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 12.690s 32.600us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.080s 147.812us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 32.610s 663.470us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 18.010s 432.960us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 11.020s 99.124us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.080s 147.812us 1 1 100.00
flash_ctrl_csr_aliasing 18.010s 432.960us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.730s 31.287us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.040s 63.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.330s 46.766us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 39.230s 1199.462us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1271.040s 167229.818us 1 1 100.00
flash_ctrl_hw_rma_reset 615.310s 160182.579us 1 1 100.00
flash_ctrl_lcmgr_intg 6.860s 77.124us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1341.420s 385509.012us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 178.000s 2091.326us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 7.440s 24.597us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2413.890s 99789.522us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 67.770s 5015.684us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.710s 56.416us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.760s 69.461us 1 1 100.00
flash_ctrl_re_evict 16.580s 62.003us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 32.050s 69.753us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 32.050s 69.753us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 157.570s 32785.789us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 19.590s 1607.262us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 91.710s 35.841us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 277.920s 8620.137us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 288.290s 1391.450us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 994.100s 4434.533us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.400s 41.940us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 123.570s 5939.345us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 8.300s 64.610us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.250s 26.442us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 187.920s 135.737us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 85.050s 3434.520us 1 1 100.00
flash_ctrl_otp_reset 49.050s 41.331us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1271.040s 167229.818us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 128.140s 2030.263us 1 1 100.00
flash_ctrl_intr_wr 53.180s 2667.760us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 222.860s 15564.086us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 152.080s 119033.250us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 49.290s 5989.919us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 34.800s 2295.704us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 15.180s 26.886us 1 1 100.00
flash_ctrl_ro_derr 96.760s 1589.753us 1 1 100.00
flash_ctrl_rw_derr 135.340s 3191.226us 1 1 100.00
flash_ctrl_derr_detect 100.560s 756.769us 1 1 100.00
flash_ctrl_integrity 427.420s 4417.630us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.420s 28.044us 1 1 100.00
flash_ctrl_ro_serr 86.540s 4139.835us 1 1 100.00
flash_ctrl_rw_serr 143.380s 3628.980us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 33.780s 847.297us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 75.170s 1366.159us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 117.900s 4229.559us 1 1 100.00
flash_ctrl_write_word_sweep 10.480s 41.685us 1 1 100.00
flash_ctrl_read_word_sweep 7.270s 31.032us 1 1 100.00
flash_ctrl_ro 77.780s 607.591us 1 1 100.00
flash_ctrl_rw 371.060s 15839.302us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 24.390s 512.835us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 573.070s 166622.717us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 71.650s 10019.382us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 7.950s 1026.377us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 7.220s 43.566us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.390s 65.387us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.390s 65.387us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.690s 32.600us 1 1 100.00
flash_ctrl_csr_rw 9.080s 147.812us 1 1 100.00
flash_ctrl_csr_aliasing 18.010s 432.960us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.340s 395.285us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.690s 32.600us 1 1 100.00
flash_ctrl_csr_rw 9.080s 147.812us 1 1 100.00
flash_ctrl_csr_aliasing 18.010s 432.960us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.340s 395.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 34.630s 48.264us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 34.630s 48.264us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 34.630s 48.264us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 34.630s 48.264us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 27.080s 1445.809us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 368.790s 1400.271us 1 1 100.00
flash_ctrl_sec_cm 1570.930s 5557.945us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 368.790s 1400.271us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 368.790s 1400.271us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 17.330s 89.034us 1 1 100.00
flash_ctrl_wr_intg 6.710s 46.517us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 32.020s 132.141us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 49.050s 41.331us 1 1 100.00
flash_ctrl_disable 8.300s 64.610us 1 1 100.00
flash_ctrl_sec_info_access 41.630s 10247.983us 1 1 100.00
flash_ctrl_connect 7.250s 26.442us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.860s 48.747us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.080s 147.812us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 34.630s 48.264us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.080s 147.812us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 34.630s 48.264us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.080s 147.812us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 34.630s 48.264us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 8.300s 64.610us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 17.330s 89.034us 1 1 100.00
flash_ctrl_access_after_disable 6.490s 51.974us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 11.230s 28.546us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 8.300s 64.610us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 19.590s 1607.262us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 371.060s 15839.302us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 143.380s 3628.980us 1 1 100.00
flash_ctrl_rw_derr 135.340s 3191.226us 1 1 100.00
flash_ctrl_integrity 427.420s 4417.630us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1271.040s 167229.818us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1570.930s 5557.945us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1570.930s 5557.945us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1570.930s 5557.945us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1570.930s 5557.945us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 6.420s 937.582us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 8.620s 20.387us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.450s 72.322us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1570.930s 5557.945us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1570.930s 5557.945us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1570.930s 5557.945us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 16.950s 53.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 61.460s 224.752us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
flash_ctrl_phy_host_grant_err 6925104145762751646108833921843151687614385466863087306996095921964467019633 122
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
UVM_ERROR @ 20387.4 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 20387.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---