Simulation Results: hmac

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.34 %
  • code
  • 97.38 %
  • assert
  • 96.42 %
  • func
  • 44.23 %
  • line
  • 99.74 %
  • branch
  • 99.50 %
  • cond
  • 96.46 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 1.480s 28.319us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.770s 67.854us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.910s 13.990us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.020s 1100.001us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.730s 1434.223us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.920s 51.371us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.910s 13.990us 1 1 100.00
hmac_csr_aliasing 4.730s 1434.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 22.760s 423.403us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 48.290s 4669.586us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 166.740s 36249.024us 1 1 100.00
hmac_test_sha384_vectors 424.300s 45466.689us 1 1 100.00
hmac_test_sha512_vectors 20.720s 235.808us 1 1 100.00
hmac_test_hmac256_vectors 7.750s 530.207us 1 1 100.00
hmac_test_hmac384_vectors 9.220s 299.626us 1 1 100.00
hmac_test_hmac512_vectors 8.060s 248.679us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 16.440s 2524.070us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 733.350s 19972.571us 1 1 100.00
error 1 1 100.00
hmac_error 14.750s 1446.804us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 65.490s 8584.814us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 1.480s 28.319us 1 1 100.00
hmac_long_msg 22.760s 423.403us 1 1 100.00
hmac_back_pressure 48.290s 4669.586us 1 1 100.00
hmac_datapath_stress 733.350s 19972.571us 1 1 100.00
hmac_burst_wr 16.440s 2524.070us 1 1 100.00
hmac_stress_all 839.210s 34836.675us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 1.480s 28.319us 1 1 100.00
hmac_long_msg 22.760s 423.403us 1 1 100.00
hmac_back_pressure 48.290s 4669.586us 1 1 100.00
hmac_datapath_stress 733.350s 19972.571us 1 1 100.00
hmac_wipe_secret 65.490s 8584.814us 1 1 100.00
hmac_test_sha256_vectors 166.740s 36249.024us 1 1 100.00
hmac_test_sha384_vectors 424.300s 45466.689us 1 1 100.00
hmac_test_sha512_vectors 20.720s 235.808us 1 1 100.00
hmac_test_hmac256_vectors 7.750s 530.207us 1 1 100.00
hmac_test_hmac384_vectors 9.220s 299.626us 1 1 100.00
hmac_test_hmac512_vectors 8.060s 248.679us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 1.480s 28.319us 1 1 100.00
hmac_long_msg 22.760s 423.403us 1 1 100.00
hmac_back_pressure 48.290s 4669.586us 1 1 100.00
hmac_datapath_stress 733.350s 19972.571us 1 1 100.00
hmac_burst_wr 16.440s 2524.070us 1 1 100.00
hmac_error 14.750s 1446.804us 1 1 100.00
hmac_wipe_secret 65.490s 8584.814us 1 1 100.00
hmac_test_sha256_vectors 166.740s 36249.024us 1 1 100.00
hmac_test_sha384_vectors 424.300s 45466.689us 1 1 100.00
hmac_test_sha512_vectors 20.720s 235.808us 1 1 100.00
hmac_test_hmac256_vectors 7.750s 530.207us 1 1 100.00
hmac_test_hmac384_vectors 9.220s 299.626us 1 1 100.00
hmac_test_hmac512_vectors 8.060s 248.679us 1 1 100.00
hmac_stress_all 839.210s 34836.675us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 839.210s 34836.675us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.810s 59.674us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.630s 19.691us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.090s 281.080us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.090s 281.080us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.770s 67.854us 1 1 100.00
hmac_csr_rw 0.910s 13.990us 1 1 100.00
hmac_csr_aliasing 4.730s 1434.223us 1 1 100.00
hmac_same_csr_outstanding 1.900s 184.292us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.770s 67.854us 1 1 100.00
hmac_csr_rw 0.910s 13.990us 1 1 100.00
hmac_csr_aliasing 4.730s 1434.223us 1 1 100.00
hmac_same_csr_outstanding 1.900s 184.292us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.930s 37.635us 1 1 100.00
hmac_tl_intg_err 3.610s 1110.658us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.610s 1110.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 1.480s 28.319us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.860s 272.050us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 54.150s 9246.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.830s 23.264us 1 1 100.00

Error Messages

   Test seed line log context