Simulation Results: i2c

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.71 %
  • code
  • 81.24 %
  • assert
  • 96.19 %
  • func
  • 79.70 %
  • line
  • 96.38 %
  • branch
  • 92.26 %
  • cond
  • 84.89 %
  • toggle
  • 89.24 %
  • FSM
  • 43.45 %
Validation stages
V1
100.00%
V2
89.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 12.710s 2258.097us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 18.650s 889.460us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.680s 21.766us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.710s 29.210us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.110s 1301.081us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.580s 141.488us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.090s 53.121us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.710s 29.210us 1 1 100.00
i2c_csr_aliasing 1.580s 141.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.910s 4.406us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 189.240s 3637.143us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 255.090s 25473.594us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.950s 81.493us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 67.000s 28682.366us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 89.000s 4362.287us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.330s 606.277us 1 1 100.00
i2c_host_fifo_fmt_empty 6.930s 1839.604us 1 1 100.00
i2c_host_fifo_reset_rx 3.790s 241.913us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 50.810s 21114.366us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 13.980s 818.804us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 6.950s 180.042us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 2.850s 1727.564us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 21.200s 79494.960us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 5.300s 701.142us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 23.830s 1897.770us 1 1 100.00
i2c_target_intr_smoke 5.500s 4404.542us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.690s 1420.735us 1 1 100.00
i2c_target_fifo_reset_tx 1.400s 233.373us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 496.890s 49393.676us 1 1 100.00
i2c_target_stress_rd 23.830s 1897.770us 1 1 100.00
i2c_target_intr_stress_wr 151.160s 15490.380us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.080s 5348.838us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 5.230s 2374.210us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 5.110s 9626.697us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 23.050s 10003.975us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.920s 822.238us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.090s 130.134us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 255.090s 25473.594us 1 1 100.00
i2c_host_perf_precise 107.270s 5862.100us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 13.980s 818.804us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.910s 138.927us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 2.940s 584.989us 1 1 100.00
i2c_target_nack_acqfull_addr 3.020s 1683.857us 1 1 100.00
i2c_target_nack_txstretch 1.480s 787.630us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 11.400s 861.292us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 2.570s 746.937us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.640s 61.050us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.660s 17.405us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.390s 66.969us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.390s 66.969us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.680s 21.766us 1 1 100.00
i2c_csr_rw 0.710s 29.210us 1 1 100.00
i2c_csr_aliasing 1.580s 141.488us 1 1 100.00
i2c_same_csr_outstanding 1.050s 116.795us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.680s 21.766us 1 1 100.00
i2c_csr_rw 0.710s 29.210us 1 1 100.00
i2c_csr_aliasing 1.580s 141.488us 1 1 100.00
i2c_same_csr_outstanding 1.050s 116.795us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.210s 131.638us 1 1 100.00
i2c_sec_cm 1.040s 167.714us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.210s 131.638us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 12.930s 587.695us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.820s 238.563us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 11.310s 2838.769us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 22994736682214654412780371387882469892856742798266002410511681652158684737729 83
UVM_ERROR @ 4405503 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 4405503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 97134419425347583051160830605633502594891644363509527693962281252865196873981 129
UVM_ERROR @ 3637142884 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 3637142884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 45515132931316760664840536770648260341105068575468261627550583901969274427162 81
UVM_ERROR @ 1727563991 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1727563991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 42763586468040031056633049737194969942519392261209948492529025189338806735938 75
UVM_ERROR @ 238563080 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 238563080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 100846018891346397763243741899377640346553504488254744079966120514240850455096 76
UVM_FATAL @ 10003975289 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10003975289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 80793013496985068057714792200295471623262935808089251340527884912096761117047 96
UVM_ERROR @ 587694642 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 587694642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 52788522273136650829751734024761876901763705197319238893660787672547081902098 84
UVM_ERROR @ 2838768647 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2838768647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 61476284422810918180167118498595513294480843830004452153180281852700327375056 75
UVM_ERROR @ 787629956 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 787629956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---