Simulation Results: keymgr

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.86 %
  • code
  • 92.03 %
  • assert
  • 97.49 %
  • func
  • 56.07 %
  • line
  • 98.66 %
  • branch
  • 97.58 %
  • cond
  • 93.05 %
  • toggle
  • 84.80 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.190s 63.237us 1 1 100.00
random 1 1 100.00
keymgr_random 2.460s 105.098us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.960s 164.799us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.960s 71.584us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 4.890s 132.034us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 9.390s 2595.133us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.190s 32.025us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.960s 71.584us 1 1 100.00
keymgr_csr_aliasing 9.390s 2595.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 4.790s 273.205us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 9.280s 578.426us 1 1 100.00
keymgr_sideload_kmac 5.420s 215.578us 1 1 100.00
keymgr_sideload_aes 3.220s 1594.911us 1 1 100.00
keymgr_sideload_otbn 3.250s 143.235us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.320s 100.838us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 1.860s 73.002us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.530s 476.529us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.770s 242.106us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.080s 38.033us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 2.160s 469.622us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 5.710s 278.162us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.760s 17.961us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.690s 38.630us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.860s 108.049us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.860s 108.049us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.960s 164.799us 1 1 100.00
keymgr_csr_rw 0.960s 71.584us 1 1 100.00
keymgr_csr_aliasing 9.390s 2595.133us 1 1 100.00
keymgr_same_csr_outstanding 1.660s 45.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.960s 164.799us 1 1 100.00
keymgr_csr_rw 0.960s 71.584us 1 1 100.00
keymgr_csr_aliasing 9.390s 2595.133us 1 1 100.00
keymgr_same_csr_outstanding 1.660s 45.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 4.330s 1010.425us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 4.330s 1010.425us 1 1 100.00
keymgr_tl_intg_err 6.140s 1043.597us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 1.270s 277.615us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 1.270s 277.615us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 1.270s 277.615us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 1.270s 277.615us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 10.580s 1261.950us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 4.330s 1010.425us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 4.330s 1010.425us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 6.140s 1043.597us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 1.270s 277.615us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 4.790s 273.205us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 2.460s 105.098us 1 1 100.00
keymgr_csr_rw 0.960s 71.584us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 2.460s 105.098us 1 1 100.00
keymgr_csr_rw 0.960s 71.584us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 2.460s 105.098us 1 1 100.00
keymgr_csr_rw 0.960s 71.584us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 1.860s 73.002us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.080s 38.033us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.080s 38.033us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.460s 105.098us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.430s 416.294us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.330s 1010.425us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.330s 1010.425us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 4.330s 1010.425us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 5.730s 410.115us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 1.860s 73.002us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 4.330s 1010.425us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.330s 1010.425us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 4.330s 1010.425us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 5.730s 410.115us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 5.730s 410.115us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 4.330s 1010.425us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 5.730s 410.115us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.330s 1010.425us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 5.730s 410.115us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 3.380s 325.595us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 85733957889693911936738933522577197193132169897422309905679220272530664316720 390
UVM_ERROR @ 325594609 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 325594609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---