Simulation Results: lc_ctrl

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.84 %
  • code
  • 83.77 %
  • assert
  • 94.13 %
  • func
  • 88.61 %
  • line
  • 97.04 %
  • branch
  • 93.67 %
  • cond
  • 79.03 %
  • toggle
  • 81.02 %
  • FSM
  • 68.09 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 5.020s 185.631us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.850s 31.541us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.890s 27.447us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 67.139us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 42.893us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.030s 46.254us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.890s 27.447us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 42.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.090s 99.214us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 13.890s 1494.763us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.750s 14.009us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.360s 234.616us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.360s 3.292us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.100s 5186.937us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.360s 3.292us 0 1 0.00
lc_ctrl_prog_failure 2.360s 234.616us 1 1 100.00
lc_ctrl_errors 6.100s 5186.937us 1 1 100.00
lc_ctrl_security_escalation 5.460s 218.473us 1 1 100.00
lc_ctrl_jtag_state_failure 10.850s 1789.350us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.230s 870.034us 1 1 100.00
lc_ctrl_jtag_errors 18.600s 4044.898us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.910s 152.631us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.370s 1497.032us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.230s 870.034us 1 1 100.00
lc_ctrl_jtag_errors 18.600s 4044.898us 1 1 100.00
lc_ctrl_jtag_access 4.540s 2864.413us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.280s 5431.815us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.260s 328.817us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.520s 79.954us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 18.780s 2277.541us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.670s 986.899us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.210s 22.195us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.700s 63.197us 1 1 100.00
lc_ctrl_jtag_alert_test 1.370s 48.433us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.660s 728.544us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.790s 102.215us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 1.930s 21.813us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.130s 80.826us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.450s 169.992us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.450s 169.992us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.850s 31.541us 1 1 100.00
lc_ctrl_csr_rw 0.890s 27.447us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 42.893us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.810s 161.181us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.850s 31.541us 1 1 100.00
lc_ctrl_csr_rw 0.890s 27.447us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 42.893us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.810s 161.181us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.230s 128.834us 1 1 100.00
lc_ctrl_tl_intg_err 2.510s 449.785us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.510s 449.785us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 13.890s 1494.763us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.360s 3.292us 0 1 0.00
lc_ctrl_sec_cm 8.230s 128.834us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.360s 3.292us 0 1 0.00
lc_ctrl_sec_cm 8.230s 128.834us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.360s 3.292us 0 1 0.00
lc_ctrl_sec_cm 8.230s 128.834us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.360s 3.292us 0 1 0.00
lc_ctrl_sec_cm 8.230s 128.834us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.360s 3.292us 0 1 0.00
lc_ctrl_sec_cm 8.230s 128.834us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.360s 3.292us 0 1 0.00
lc_ctrl_sec_cm 8.230s 128.834us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.360s 3.292us 0 1 0.00
lc_ctrl_sec_cm 8.230s 128.834us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.360s 3.292us 0 1 0.00
lc_ctrl_sec_cm 8.230s 128.834us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.460s 218.473us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.090s 99.214us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.370s 1497.032us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.500s 948.303us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.500s 948.303us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.070s 1297.287us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.920s 1052.126us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.920s 1052.126us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 9.240s 4385.389us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 72462670321176424745376816330719902771488266411458685576343764269902789671324 123
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3291979 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3291979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 16752696876863137033721602597601194329464946534594477153372763598410611360419 1432
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1789350167 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1789350167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 25488993789131709923138058796207145907087636761705673571460232228476630220364 282
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 21812853 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 21812853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 103844185281907756337290862782556584887290547566289120841910811360640477780724 836
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 4385389056 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 4385389056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---