Simulation Results: lc_ctrl

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.23 %
  • code
  • 83.55 %
  • assert
  • 94.13 %
  • func
  • 87.01 %
  • line
  • 96.97 %
  • branch
  • 93.32 %
  • cond
  • 79.21 %
  • toggle
  • 80.89 %
  • FSM
  • 67.37 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.560s 133.476us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.990s 81.085us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.810s 19.494us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.060s 21.244us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 39.311us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.190s 79.316us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.810s 19.494us 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 39.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.960s 64.910us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.800s 236.921us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.850s 99.147us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.410s 67.415us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3.230s 246.340us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.130s 217.264us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 3.230s 246.340us 0 1 0.00
lc_ctrl_prog_failure 1.410s 67.415us 1 1 100.00
lc_ctrl_errors 5.130s 217.264us 1 1 100.00
lc_ctrl_security_escalation 3.460s 187.168us 1 1 100.00
lc_ctrl_jtag_state_failure 1.780s 395.518us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.740s 1247.568us 1 1 100.00
lc_ctrl_jtag_errors 17.580s 7085.148us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 4.030s 683.937us 1 1 100.00
lc_ctrl_jtag_state_post_trans 1.440s 238.668us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.740s 1247.568us 1 1 100.00
lc_ctrl_jtag_errors 17.580s 7085.148us 1 1 100.00
lc_ctrl_jtag_access 8.350s 870.592us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.830s 1520.482us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.460s 113.866us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.420s 926.612us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.060s 4456.357us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.060s 3196.576us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.560s 29.411us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.330s 228.366us 1 1 100.00
lc_ctrl_jtag_alert_test 1.230s 149.062us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.960s 602.923us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.940s 15.358us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 22.470s 7105.221us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 165.693us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.950s 129.966us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.950s 129.966us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.990s 81.085us 1 1 100.00
lc_ctrl_csr_rw 0.810s 19.494us 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 39.311us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.240s 38.795us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.990s 81.085us 1 1 100.00
lc_ctrl_csr_rw 0.810s 19.494us 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 39.311us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.240s 38.795us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.080s 236.759us 1 1 100.00
lc_ctrl_tl_intg_err 1.230s 162.197us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.230s 162.197us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.800s 236.921us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3.230s 246.340us 0 1 0.00
lc_ctrl_sec_cm 8.080s 236.759us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3.230s 246.340us 0 1 0.00
lc_ctrl_sec_cm 8.080s 236.759us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.230s 246.340us 0 1 0.00
lc_ctrl_sec_cm 8.080s 236.759us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.230s 246.340us 0 1 0.00
lc_ctrl_sec_cm 8.080s 236.759us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3.230s 246.340us 0 1 0.00
lc_ctrl_sec_cm 8.080s 236.759us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.230s 246.340us 0 1 0.00
lc_ctrl_sec_cm 8.080s 236.759us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.230s 246.340us 0 1 0.00
lc_ctrl_sec_cm 8.080s 236.759us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3.230s 246.340us 0 1 0.00
lc_ctrl_sec_cm 8.080s 236.759us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.460s 187.168us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3.960s 64.910us 1 1 100.00
lc_ctrl_jtag_state_post_trans 1.440s 238.668us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.820s 907.848us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.820s 907.848us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.350s 908.959us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.130s 916.162us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.130s 916.162us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 10.970s 966.448us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 1739241132283248841693779974563477914942321771488079400489010184241515178755 355
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 246339643 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 246339643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 8465655599263891597700323742551684997475066676059355745725571941861799320024 194
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 395518312 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 395518312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 68604521193675626216183546591998227305962875455637110166910756397868913408284 194
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 238668390 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 238668390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 102163588657793120955994701773751808822410067763101543529765494384071593058965 2932
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 7105220700 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 7105220700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 83427643400314564418927146586013723054932991654061891201001762280031853340281 685
UVM_ERROR @ 966448124 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 966448124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---