Simulation Results: otp_ctrl

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.87 %
  • code
  • 75.81 %
  • assert
  • 93.06 %
  • func
  • 67.73 %
  • line
  • 88.17 %
  • branch
  • 82.98 %
  • cond
  • 89.63 %
  • toggle
  • 77.84 %
  • FSM
  • 40.45 %
Validation stages
V1
90.91%
V2
84.00%
V2S
92.86%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.470s 59.729us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.930s 915.574us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.860s 103.532us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.460s 108.190us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.940s 342.862us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.770s 189.283us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.640s 52.139us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.460s 108.190us 1 1 100.00
otp_ctrl_csr_aliasing 2.770s 189.283us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.660s 88.635us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.190s 75.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.180s 1075.083us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.860s 1705.515us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 3.470s 367.607us 0 1 0.00
otp_ctrl_check_fail 5.810s 4372.394us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.450s 289.920us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 16.530s 1536.033us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 19.690s 2119.639us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 6.470s 206.163us 1 1 100.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 9.530s 580.599us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 11.150s 660.206us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 5.430s 231.413us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 41.710s 4708.220us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.320s 112.763us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.220s 56.975us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.790s 98.124us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.790s 98.124us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.860s 103.532us 1 1 100.00
otp_ctrl_csr_rw 1.460s 108.190us 1 1 100.00
otp_ctrl_csr_aliasing 2.770s 189.283us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.580s 91.710us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.860s 103.532us 1 1 100.00
otp_ctrl_csr_rw 1.460s 108.190us 1 1 100.00
otp_ctrl_csr_aliasing 2.770s 189.283us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.580s 91.710us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 16.200s 4482.648us 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 16.200s 4482.648us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.930s 915.574us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.930s 915.574us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
otp_ctrl_macro_errs 11.150s 660.206us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
otp_ctrl_macro_errs 11.150s 660.206us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.850s 4570.299us 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.860s 1705.515us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 5.810s 4372.394us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 16.530s 1536.033us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 16.530s 1536.033us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 16.530s 1536.033us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 16.530s 1536.033us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 16.530s 1536.033us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.930s 915.574us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 16.530s 1536.033us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.930s 915.574us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 108.200s 20764.946us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.450s 289.920us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.930s 915.574us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.930s 915.574us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 11.150s 660.206us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 13.450s 5897.491us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.320s 113.672us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_csr_mem_rw_with_rand_reset 48216078160173134976776553801375789202628383869065785169246209855213453704432 89
UVM_ERROR @ 52138850 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 52138850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38843777965385143483564135204485737665417835004241370519509775409745198920507 89
UVM_ERROR @ 113671526 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 113671526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1308) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 4994561342062858976729812404782243054010511846779239443206925822037149089567 967
UVM_ERROR @ 367607497 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 367607497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 64111103527242557295716109303675504591773235330534862347687929217380528345357 43039
UVM_ERROR @ 4708220326 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 4708220326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 84620773565103955379874398514466866554319929867589287103059929157881430499087 4321
UVM_ERROR @ 4372394252 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1697996845 [0x6535602d] vs 1697988653 [0x6535402d]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 4372394252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 11871328644978430346513294780648282522520738034351320017824367782840972966030 7564
UVM_ERROR @ 660206417 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2134322623 [0x7f372dbf] vs 2134322367 [0x7f372cbf]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 660206417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---