Simulation Results: pattgen

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
93.75%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 187.768us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 12.288us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 15.637us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 285.195us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 12.978us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 105.193us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 15.637us 1 1 100.00
pattgen_csr_aliasing 1.000s 12.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 35.000s 1345.052us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 9.000s 1324.846us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 67.656us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 2.000s 195.550us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 41.115us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 136.712us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 283.893us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 283.893us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 12.288us 1 1 100.00
pattgen_csr_rw 1.000s 15.637us 1 1 100.00
pattgen_csr_aliasing 1.000s 12.978us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 50.235us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 12.288us 1 1 100.00
pattgen_csr_rw 1.000s 15.637us 1 1 100.00
pattgen_csr_aliasing 1.000s 12.978us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 50.235us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 2.000s 42.281us 1 1 100.00
pattgen_sec_cm 2.000s 268.451us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 42.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
pattgen_stress_all_with_rand_reset 21.000s 4446.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 3.000s 189.868us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:
pattgen_stress_all 96390016870444056367941757541433061589748179184426591687718528675297275103951 150
UVM_ERROR @ 195549832 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10351