Simulation Results: pwm

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.96 %
  • code
  • 95.18 %
  • assert
  • 98.00 %
  • func
  • 97.69 %
  • block
  • 99.15 %
  • line
  • 99.40 %
  • branch
  • 98.53 %
  • toggle
  • 87.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwm_smoke 3.000s 622.691us 1 1 100.00
csr_hw_reset 1 1 100.00
pwm_csr_hw_reset 1.000s 67.753us 1 1 100.00
csr_rw 1 1 100.00
pwm_csr_rw 1.000s 15.167us 1 1 100.00
csr_bit_bash 1 1 100.00
pwm_csr_bit_bash 4.000s 201.893us 1 1 100.00
csr_aliasing 1 1 100.00
pwm_csr_aliasing 2.000s 65.062us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwm_csr_mem_rw_with_rand_reset 2.000s 117.894us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwm_csr_rw 1.000s 15.167us 1 1 100.00
pwm_csr_aliasing 2.000s 65.062us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dutycycle 1 1 100.00
pwm_rand_output 35.000s 10717.197us 1 1 100.00
pulse 1 1 100.00
pwm_rand_output 35.000s 10717.197us 1 1 100.00
blink 1 1 100.00
pwm_rand_output 35.000s 10717.197us 1 1 100.00
heartbeat 1 1 100.00
pwm_rand_output 35.000s 10717.197us 1 1 100.00
resolution 1 1 100.00
pwm_rand_output 35.000s 10717.197us 1 1 100.00
multi_channel 1 1 100.00
pwm_rand_output 35.000s 10717.197us 1 1 100.00
polarity 1 1 100.00
pwm_rand_output 35.000s 10717.197us 1 1 100.00
phase 2 2 100.00
pwm_rand_output 35.000s 10717.197us 1 1 100.00
pwm_phase 30.000s 21878.969us 1 1 100.00
lowpower 1 1 100.00
pwm_rand_output 35.000s 10717.197us 1 1 100.00
perf 1 1 100.00
pwm_perf 36.000s 10721.154us 1 1 100.00
regwen 1 1 100.00
pwm_regwen 114.000s 43731.238us 1 1 100.00
stress_all 1 1 100.00
pwm_stress_all 43.000s 52195.841us 1 1 100.00
alert_test 1 1 100.00
pwm_alert_test 1.000s 22.783us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwm_tl_errors 2.000s 515.768us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwm_tl_errors 2.000s 515.768us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwm_csr_hw_reset 1.000s 67.753us 1 1 100.00
pwm_csr_rw 1.000s 15.167us 1 1 100.00
pwm_csr_aliasing 2.000s 65.062us 1 1 100.00
pwm_same_csr_outstanding 2.000s 176.758us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwm_csr_hw_reset 1.000s 67.753us 1 1 100.00
pwm_csr_rw 1.000s 15.167us 1 1 100.00
pwm_csr_aliasing 2.000s 65.062us 1 1 100.00
pwm_same_csr_outstanding 2.000s 176.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwm_tl_intg_err 1.000s 199.714us 1 1 100.00
pwm_sec_cm 1.000s 95.165us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwm_tl_intg_err 1.000s 199.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
heartbeat_wrap 1 1 100.00
pwm_heartbeat_wrap 30.000s 42003.322us 1 1 100.00

Error Messages

   Test seed line log context