| V1 |
|
100.00% |
| V2 |
|
95.45% |
| V2S |
|
52.94% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| pwrmgr_smoke | 0.900s | 52.845us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| pwrmgr_csr_hw_reset | 0.840s | 28.062us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| pwrmgr_csr_rw | 0.730s | 20.759us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| pwrmgr_csr_bit_bash | 2.480s | 2039.036us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| pwrmgr_csr_aliasing | 0.740s | 87.543us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| pwrmgr_csr_mem_rw_with_rand_reset | 0.910s | 51.969us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| pwrmgr_csr_rw | 0.730s | 20.759us | 1 | 1 | 100.00 | |
| pwrmgr_csr_aliasing | 0.740s | 87.543us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wakeup | 1 | 1 | 100.00 | |||
| pwrmgr_wakeup | 0.930s | 328.059us | 1 | 1 | 100.00 | |
| control_clks | 1 | 1 | 100.00 | |||
| pwrmgr_wakeup | 0.930s | 328.059us | 1 | 1 | 100.00 | |
| aborted_low_power | 2 | 2 | 100.00 | |||
| pwrmgr_aborted_low_power | 0.670s | 102.867us | 1 | 1 | 100.00 | |
| pwrmgr_lowpower_invalid | 0.810s | 46.586us | 1 | 1 | 100.00 | |
| reset | 2 | 2 | 100.00 | |||
| pwrmgr_reset | 0.920s | 32.527us | 1 | 1 | 100.00 | |
| pwrmgr_reset_invalid | 0.930s | 174.691us | 1 | 1 | 100.00 | |
| main_power_glitch_reset | 1 | 1 | 100.00 | |||
| pwrmgr_reset | 0.920s | 32.527us | 1 | 1 | 100.00 | |
| reset_wakeup_race | 1 | 1 | 100.00 | |||
| pwrmgr_wakeup_reset | 1.090s | 311.700us | 1 | 1 | 100.00 | |
| lowpower_wakeup_race | 1 | 1 | 100.00 | |||
| pwrmgr_lowpower_wakeup_race | 1.100s | 266.740us | 1 | 1 | 100.00 | |
| disable_rom_integrity_check | 0 | 1 | 0.00 | |||
| pwrmgr_disable_rom_integrity_check | 1.550s | 1000.000us | 0 | 1 | 0.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| pwrmgr_stress_all | 4.750s | 1754.599us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| pwrmgr_intr_test | 0.760s | 42.582us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| pwrmgr_tl_errors | 1.780s | 184.047us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| pwrmgr_tl_errors | 1.780s | 184.047us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| pwrmgr_csr_hw_reset | 0.840s | 28.062us | 1 | 1 | 100.00 | |
| pwrmgr_csr_rw | 0.730s | 20.759us | 1 | 1 | 100.00 | |
| pwrmgr_csr_aliasing | 0.740s | 87.543us | 1 | 1 | 100.00 | |
| pwrmgr_same_csr_outstanding | 0.730s | 75.589us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| pwrmgr_csr_hw_reset | 0.840s | 28.062us | 1 | 1 | 100.00 | |
| pwrmgr_csr_rw | 0.730s | 20.759us | 1 | 1 | 100.00 | |
| pwrmgr_csr_aliasing | 0.740s | 87.543us | 1 | 1 | 100.00 | |
| pwrmgr_same_csr_outstanding | 0.730s | 75.589us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| pwrmgr_sec_cm | 0.700s | 25.692us | 0 | 1 | 0.00 | |
| pwrmgr_tl_intg_err | 0.730s | 7.652us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.700s | 25.692us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.700s | 25.692us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| pwrmgr_tl_intg_err | 0.730s | 7.652us | 0 | 1 | 0.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 1 | 1 | 100.00 | |||
| pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 2.660s | 830.717us | 1 | 1 | 100.00 | |
| sec_cm_rom_ctrl_intersig_mubi | 1 | 1 | 100.00 | |||
| pwrmgr_wakeup_reset | 1.090s | 311.700us | 1 | 1 | 100.00 | |
| sec_cm_rstmgr_intersig_mubi | 1 | 1 | 100.00 | |||
| pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.800s | 45.887us | 1 | 1 | 100.00 | |
| sec_cm_esc_rx_clk_bkgn_chk | 1 | 1 | 100.00 | |||
| pwrmgr_esc_clk_rst_malfunc | 0.700s | 43.921us | 1 | 1 | 100.00 | |
| sec_cm_esc_rx_clk_local_esc | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.700s | 25.692us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.700s | 25.692us | 0 | 1 | 0.00 | |
| sec_cm_fsm_terminal | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.700s | 25.692us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_flow_global_esc | 1 | 1 | 100.00 | |||
| pwrmgr_global_esc | 0.920s | 150.102us | 1 | 1 | 100.00 | |
| sec_cm_main_pd_rst_local_esc | 1 | 1 | 100.00 | |||
| pwrmgr_glitch | 0.700s | 50.409us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| pwrmgr_sec_cm_ctrl_config_regwen | 1.210s | 311.442us | 1 | 1 | 100.00 | |
| sec_cm_wakeup_config_regwen | 1 | 1 | 100.00 | |||
| pwrmgr_csr_rw | 0.730s | 20.759us | 1 | 1 | 100.00 | |
| sec_cm_reset_config_regwen | 1 | 1 | 100.00 | |||
| pwrmgr_csr_rw | 0.730s | 20.759us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| escalation_timeout | 0 | 1 | 0.00 | |||
| pwrmgr_escalation_timeout | 0.910s | 653.924us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| pwrmgr_stress_all_with_rand_reset | 8.830s | 12494.247us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A | ||||
| pwrmgr_escalation_timeout | 96316313767851733429094635052382355691460522516938884308890641036263110819025 | 72 |
UVM_ERROR @ 653923693 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 653923693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | ||||
| pwrmgr_disable_rom_integrity_check | 30502285685840163270538088021081032381705408422003294454413691478373004202465 | 131 |
UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire | ||||
| pwrmgr_sec_cm | 95685139595642573966590938351313310176135946244639472877038162889637883776521 | 77 |
UVM_ERROR @ 25691908 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 25691908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 90415558315999306453165859558895248527837332890702377957446813908743481124653 | 82 |
UVM_ERROR @ 7652048 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 7652048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:454) [pwrmgr_common_vseq] wait timeout occurred! | ||||
| pwrmgr_stress_all_with_rand_reset | 61335486384667466190203774338734594100888082385727917069836219206393437081803 | 1076 |
UVM_FATAL @ 12494247449 ps: (cip_base_vseq.sv:454) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
UVM_INFO @ 12494247449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|