Simulation Results: rom_ctrl

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.68 %
  • code
  • 98.12 %
  • assert
  • 95.49 %
  • func
  • 96.42 %
  • line
  • 99.46 %
  • branch
  • 97.81 %
  • cond
  • 93.76 %
  • toggle
  • 99.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.350s 986.776us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.500s 1078.511us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.160s 788.144us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.350s 383.322us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.540s 470.919us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.280s 218.029us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.160s 788.144us 1 1 100.00
rom_ctrl_csr_aliasing 6.540s 470.919us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.690s 212.696us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.240s 1069.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.260s 1013.298us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 28.680s 2785.987us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 18.090s 2190.201us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.300s 953.869us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.850s 700.250us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.850s 700.250us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.500s 1078.511us 1 1 100.00
rom_ctrl_csr_rw 5.160s 788.144us 1 1 100.00
rom_ctrl_csr_aliasing 6.540s 470.919us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.370s 2514.571us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.500s 1078.511us 1 1 100.00
rom_ctrl_csr_rw 5.160s 788.144us 1 1 100.00
rom_ctrl_csr_aliasing 6.540s 470.919us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.370s 2514.571us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.550s 21599.009us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 38.410s 6377.844us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 223.370s 1940.279us 0 1 0.00
rom_ctrl_tl_intg_err 94.320s 401.628us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 223.370s 1940.279us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 223.370s 1940.279us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.550s 21599.009us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.550s 21599.009us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.550s 21599.009us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.550s 21599.009us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.550s 21599.009us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 223.370s 1940.279us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 223.370s 1940.279us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.350s 986.776us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.350s 986.776us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.350s 986.776us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 94.320s 401.628us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.550s 21599.009us 1 1 100.00
rom_ctrl_kmac_err_chk 18.090s 2190.201us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.550s 21599.009us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.550s 21599.009us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.550s 21599.009us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 38.410s 6377.844us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 223.370s 1940.279us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 37.070s 1359.843us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 16601837834125130498898045355930358769088949530257246263465826860810749010739 119
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 33578699ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 33578699ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 33578699ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))