Simulation Results: rstmgr

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.49 %
  • code
  • 99.36 %
  • assert
  • 97.86 %
  • func
  • 98.26 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.61 %
  • toggle
  • 99.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.190s 123.986us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.980s 96.791us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.890s 71.957us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.430s 267.822us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.180s 117.359us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.290s 155.197us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.890s 71.957us 1 1 100.00
rstmgr_csr_aliasing 1.180s 117.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.940s 222.163us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.470s 258.534us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.120s 131.541us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 2.790s 792.458us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 2.790s 792.458us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 2.790s 792.458us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 2.790s 792.458us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 19.570s 6464.958us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.730s 73.439us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.390s 186.528us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.390s 186.528us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.980s 96.791us 1 1 100.00
rstmgr_csr_rw 0.890s 71.957us 1 1 100.00
rstmgr_csr_aliasing 1.180s 117.359us 1 1 100.00
rstmgr_same_csr_outstanding 1.300s 238.069us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.980s 96.791us 1 1 100.00
rstmgr_csr_rw 0.890s 71.957us 1 1 100.00
rstmgr_csr_aliasing 1.180s 117.359us 1 1 100.00
rstmgr_same_csr_outstanding 1.300s 238.069us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_tl_intg_err 1.960s 488.871us 1 1 100.00
rstmgr_sec_cm 20.590s 16980.335us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 20.590s 16980.335us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 20.590s 16980.335us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.960s 488.871us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.920s 98.571us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.830s 1284.712us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.160s 302.250us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 20.590s 16980.335us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.890s 71.957us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.890s 71.957us 1 1 100.00

Error Messages

   Test seed line log context