Simulation Results: rv_timer

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.27 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 95.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.330s 212.311us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.530s 13.370us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.590s 137.322us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.520s 386.632us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.760s 132.912us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.020s 134.710us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.590s 137.322us 1 1 100.00
rv_timer_csr_aliasing 0.760s 132.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 8.130s 15382.724us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.920s 1252.439us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.830s 215.580us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.830s 215.580us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.760s 2799.060us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.500s 14.963us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.560s 13.473us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.240s 280.861us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.240s 280.861us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.530s 13.370us 1 1 100.00
rv_timer_csr_rw 0.590s 137.322us 1 1 100.00
rv_timer_csr_aliasing 0.760s 132.912us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 104.533us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.530s 13.370us 1 1 100.00
rv_timer_csr_rw 0.590s 137.322us 1 1 100.00
rv_timer_csr_aliasing 0.760s 132.912us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 104.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.820s 1890.789us 1 1 100.00
rv_timer_tl_intg_err 0.920s 336.077us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.920s 336.077us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.690s 61.016us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.690s 43.953us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 10.550s 3871.066us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 32973878092396884323619509132727960770123554125614711068229973601963896627638 75
UVM_FATAL @ 61015905 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4cd77d04) == 0x1
UVM_INFO @ 61015905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 92931549884164581071763161766085612252440945214851207439242104703514466267108 72
UVM_FATAL @ 15382723582 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb3008704) == 0x1
UVM_INFO @ 15382723582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 49189001973757399544656633277324764351890769953530947883668916711739747132899 74
UVM_ERROR @ 43952990 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 43952990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---