Simulation Results: spi_device

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.13 %
  • code
  • 94.05 %
  • assert
  • 86.68 %
  • func
  • 65.67 %
  • line
  • 99.11 %
  • branch
  • 98.32 %
  • cond
  • 95.70 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 44.020s 5280.149us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.950s 213.961us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.610s 156.407us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.560s 183.521us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 4.630s 440.580us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.160s 44.854us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.610s 156.407us 1 1 100.00
spi_device_csr_aliasing 4.630s 440.580us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.700s 13.341us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.320s 48.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.820s 33.988us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.910s 15.899us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.690s 26.976us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.820s 66.828us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.820s 66.828us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 10.390s 5130.323us 1 1 100.00
spi_device_tpm_sts_read 0.650s 62.146us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 6.000s 1442.474us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.970s 638.356us 1 1 100.00
spi_device_flash_all 53.110s 113494.720us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.280s 1110.605us 1 1 100.00
spi_device_flash_all 53.110s 113494.720us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.280s 1110.605us 1 1 100.00
spi_device_flash_all 53.110s 113494.720us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 53.110s 113494.720us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.500s 2411.133us 1 1 100.00
spi_device_flash_all 53.110s 113494.720us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.500s 2411.133us 1 1 100.00
spi_device_flash_all 53.110s 113494.720us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.500s 2411.133us 1 1 100.00
spi_device_flash_all 53.110s 113494.720us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.500s 2411.133us 1 1 100.00
spi_device_flash_all 53.110s 113494.720us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.500s 2411.133us 1 1 100.00
spi_device_flash_all 53.110s 113494.720us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.230s 9967.327us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 6.830s 1903.824us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 6.830s 1903.824us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 6.830s 1903.824us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 8.820s 5682.639us 1 1 100.00
spi_device_read_buffer_direct 3.980s 818.844us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 6.830s 1903.824us 1 1 100.00
spi_device_flash_all 53.110s 113494.720us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 53.110s 113494.720us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 53.110s 113494.720us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.960s 375.735us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.960s 375.735us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 44.020s 5280.149us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 50.380s 13917.713us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 75.590s 38812.088us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.980s 12.695us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.730s 18.718us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.840s 137.028us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.840s 137.028us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.950s 213.961us 1 1 100.00
spi_device_csr_rw 1.610s 156.407us 1 1 100.00
spi_device_csr_aliasing 4.630s 440.580us 1 1 100.00
spi_device_same_csr_outstanding 1.440s 29.823us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.950s 213.961us 1 1 100.00
spi_device_csr_rw 1.610s 156.407us 1 1 100.00
spi_device_csr_aliasing 4.630s 440.580us 1 1 100.00
spi_device_same_csr_outstanding 1.440s 29.823us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.360s 94.824us 1 1 100.00
spi_device_tl_intg_err 9.740s 11020.628us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.740s 11020.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 16.720s 3162.841us 1 1 100.00

Error Messages

   Test seed line log context