Simulation Results: sram_ctrl

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.18 %
  • code
  • 93.80 %
  • assert
  • 95.83 %
  • func
  • 95.92 %
  • line
  • 98.48 %
  • branch
  • 96.78 %
  • cond
  • 92.53 %
  • toggle
  • 90.71 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.700s 776.124us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.660s 13.738us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.760s 52.340us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.100s 97.079us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 17.935us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.930s 1472.022us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.760s 52.340us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 17.935us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 114.180s 31545.930us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 64.150s 20510.063us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 60.910s 1748.008us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 234.330s 23990.435us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1357.890s 100972.453us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 428.150s 26160.194us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 35.060s 10124.489us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 500.040s 20218.144us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 14.750s 1251.369us 1 1 100.00
sram_ctrl_partial_access_b2b 357.680s 77834.653us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 7.510s 723.856us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.600s 3186.620us 1 1 100.00
sram_ctrl_throughput_w_readback 14.020s 1529.343us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 755.420s 39049.226us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.080s 1371.908us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1318.520s 91155.730us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.800s 29.600us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.750s 76.064us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.750s 76.064us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.660s 13.738us 1 1 100.00
sram_ctrl_csr_rw 0.760s 52.340us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 17.935us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.930s 22.200us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.660s 13.738us 1 1 100.00
sram_ctrl_csr_rw 0.760s 52.340us 1 1 100.00
sram_ctrl_csr_aliasing 0.860s 17.935us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.930s 22.200us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.340s 7615.617us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.900s 13.045us 0 1 0.00
sram_ctrl_tl_intg_err 2.140s 287.286us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.900s 13.045us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.140s 287.286us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 755.420s 39049.226us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 755.420s 39049.226us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.760s 52.340us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 500.040s 20218.144us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 500.040s 20218.144us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 500.040s 20218.144us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 35.060s 10124.489us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.590s 671.665us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.340s 7615.617us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.930s 699.002us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.700s 776.124us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.700s 776.124us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 500.040s 20218.144us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.900s 13.045us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 35.060s 10124.489us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.900s 13.045us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.900s 13.045us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.700s 776.124us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.900s 13.045us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 34.620s 3636.800us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 2921082401538271021659475718818978794092335017716339944089782322716308411042 99
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 13045243 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 13045243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---