Simulation Results: sram_ctrl

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.75 %
  • code
  • 90.15 %
  • assert
  • 95.37 %
  • func
  • 95.73 %
  • line
  • 97.58 %
  • branch
  • 95.20 %
  • cond
  • 91.19 %
  • toggle
  • 90.59 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 32.120s 564.606us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.960s 17.566us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.690s 24.250us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.100s 49.410us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.750s 29.634us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.810s 122.293us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.690s 24.250us 1 1 100.00
sram_ctrl_csr_aliasing 0.750s 29.634us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.450s 691.220us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.460s 71.608us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 339.920s 3554.020us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 218.450s 3330.984us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 58.360s 5188.375us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 846.550s 25862.978us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 1.270s 102.810us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 199.920s 21165.816us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.060s 40.944us 1 1 100.00
sram_ctrl_partial_access_b2b 169.910s 38149.953us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 7.140s 67.344us 1 1 100.00
sram_ctrl_throughput_w_partial_write 48.370s 154.009us 1 1 100.00
sram_ctrl_throughput_w_readback 40.640s 274.504us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 378.540s 57787.356us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.740s 81.022us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1172.550s 153964.097us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.930s 13.795us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.230s 23.726us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.230s 23.726us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.960s 17.566us 1 1 100.00
sram_ctrl_csr_rw 0.690s 24.250us 1 1 100.00
sram_ctrl_csr_aliasing 0.750s 29.634us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.720s 14.805us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.960s 17.566us 1 1 100.00
sram_ctrl_csr_rw 0.690s 24.250us 1 1 100.00
sram_ctrl_csr_aliasing 0.750s 29.634us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.720s 14.805us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.320s 534.172us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.890s 7.258us 0 1 0.00
sram_ctrl_tl_intg_err 1.310s 213.241us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.890s 7.258us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.310s 213.241us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 378.540s 57787.356us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 378.540s 57787.356us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.690s 24.250us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 199.920s 21165.816us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 199.920s 21165.816us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 199.920s 21165.816us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 1.270s 102.810us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 0.960s 26.283us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.320s 534.172us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.110s 117.155us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 32.120s 564.606us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 32.120s 564.606us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 199.920s 21165.816us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.890s 7.258us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 1.270s 102.810us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.890s 7.258us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.890s 7.258us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 32.120s 564.606us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.890s 7.258us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 171.430s 3352.672us 1 1 100.00

Error Messages

   Test seed line log context
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 64741520250812427044451122406336078005205143671784613782538380395896999564836 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 26282764 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 26282764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
sram_ctrl_sec_cm 107376470568024363876706572005651087601052952989508911405652363493807975480833 97
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 3918021ps failed at 3918021ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 3958021ps failed at 3958021ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'