Simulation Results: sysrst_ctrl

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.28 %
  • code
  • 93.56 %
  • assert
  • 93.30 %
  • func
  • 65.99 %
  • line
  • 97.28 %
  • branch
  • 97.52 %
  • cond
  • 94.77 %
  • toggle
  • 100.00 %
  • FSM
  • 78.21 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.760s 2117.280us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.740s 2484.441us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.900s 2437.628us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.780s 2335.379us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 1.430s 6311.180us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.700s 2028.896us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 21.350s 77302.748us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.420s 2991.918us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 6.260s 2081.157us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.700s 2028.896us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.420s 2991.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 19.400s 52631.550us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 69.600s 65493.749us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.140s 3563.384us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.850s 4606.190us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.530s 2508.566us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.420s 2053.393us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.890s 3859.174us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 6.530s 2607.936us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 7.270s 7012.123us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 16.100s 32934.171us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 155.350s 97981.851us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 3.940s 2022.409us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.800s 2018.179us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 6.270s 2150.110us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 6.270s 2150.110us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.430s 6311.180us 1 1 100.00
sysrst_ctrl_csr_rw 4.700s 2028.896us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.420s 2991.918us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.310s 7652.655us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.430s 6311.180us 1 1 100.00
sysrst_ctrl_csr_rw 4.700s 2028.896us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.420s 2991.918us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.310s 7652.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 41.200s 42035.569us 1 1 100.00
sysrst_ctrl_tl_intg_err 84.030s 42435.436us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 84.030s 42435.436us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 7.940s 7033.605us 1 1 100.00

Error Messages

   Test seed line log context