Simulation Results: uart

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.22 %
  • code
  • 96.77 %
  • assert
  • 97.12 %
  • func
  • 40.77 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.90 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.860s 87.284us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.670s 18.002us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.590s 16.360us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.080s 143.779us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.660s 24.500us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.950s 29.742us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.590s 16.360us 1 1 100.00
uart_csr_aliasing 0.660s 24.500us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 10.900s 87806.986us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.860s 87.284us 1 1 100.00
uart_tx_rx 10.900s 87806.986us 1 1 100.00
parity_error 2 2 100.00
uart_intr 161.700s 183103.671us 1 1 100.00
uart_rx_parity_err 148.370s 212073.016us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 10.900s 87806.986us 1 1 100.00
uart_intr 161.700s 183103.671us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 66.310s 68181.588us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 80.140s 91120.452us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 9.360s 62617.283us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 161.700s 183103.671us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 161.700s 183103.671us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 161.700s 183103.671us 1 1 100.00
perf 1 1 100.00
uart_perf 156.820s 19847.343us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.570s 6357.222us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.570s 6357.222us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.320s 1848.913us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 0.950s 1323.055us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 13.830s 7330.005us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 20.670s 6644.191us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 591.870s 127194.866us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 4.180s 8852.063us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.630s 44.699us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.610s 161.488us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.060s 118.976us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.060s 118.976us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.670s 18.002us 1 1 100.00
uart_csr_rw 0.590s 16.360us 1 1 100.00
uart_csr_aliasing 0.660s 24.500us 1 1 100.00
uart_same_csr_outstanding 0.620s 52.702us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.670s 18.002us 1 1 100.00
uart_csr_rw 0.590s 16.360us 1 1 100.00
uart_csr_aliasing 0.660s 24.500us 1 1 100.00
uart_same_csr_outstanding 0.620s 52.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.710s 403.237us 1 1 100.00
uart_tl_intg_err 1.070s 193.396us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.070s 193.396us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 3.420s 623.389us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_noise_filter 52139256794252495120982948649727929942839491849443973032159813424600004335836 71
UVM_ERROR @ 7661966 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 11508874 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 11508874 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 324322698 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 324322698 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 92383326468472353701059250765479331977402418063564818095432764676889099377897 94
UVM_ERROR @ 591838296 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 596450504 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 596736216 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 597838248 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 606940216 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0