Simulation Results: adc_ctrl

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.09 %
  • code
  • 95.98 %
  • assert
  • 95.95 %
  • func
  • 45.34 %
  • line
  • 99.02 %
  • branch
  • 98.58 %
  • cond
  • 95.82 %
  • toggle
  • 100.00 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.800s 5584.544us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 3.040s 1237.839us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.050s 522.912us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 32.140s 26683.391us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.670s 936.450us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.480s 368.894us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.050s 522.912us 1 1 100.00
adc_ctrl_csr_aliasing 1.670s 936.450us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 804.620s 504926.744us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 409.700s 486943.595us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 663.540s 492615.887us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 123.410s 162671.522us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 83.500s 182731.335us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 55.920s 210577.625us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 556.540s 329531.779us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 65.430s 166949.844us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 8.340s 2993.437us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 21.830s 26988.421us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 53.300s 90362.351us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 267.880s 354396.604us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.030s 482.106us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.100s 353.238us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 3.870s 617.487us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 3.870s 617.487us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.040s 1237.839us 1 1 100.00
adc_ctrl_csr_rw 1.050s 522.912us 1 1 100.00
adc_ctrl_csr_aliasing 1.670s 936.450us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.220s 4740.254us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.040s 1237.839us 1 1 100.00
adc_ctrl_csr_rw 1.050s 522.912us 1 1 100.00
adc_ctrl_csr_aliasing 1.670s 936.450us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.220s 4740.254us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_tl_intg_err 4.300s 9515.282us 1 1 100.00
adc_ctrl_sec_cm 8.130s 4303.786us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 4.300s 9515.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 9.670s 22123.809us 1 1 100.00

Error Messages

   Test seed line log context