Simulation Results: chip

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.21 %
  • code
  • 85.72 %
  • assert
  • 96.60 %
  • func
  • 31.30 %
  • line
  • 94.52 %
  • branch
  • 94.31 %
  • cond
  • 91.22 %
  • toggle
  • 91.43 %
  • FSM
  • 57.14 %
Validation stages
V1
95.65%
V2
87.75%
V2S
100.00%
V3
70.00%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 138.800s 3434.141us 1 1 100.00
chip_sw_example_rom 51.090s 1882.951us 1 1 100.00
chip_sw_example_manufacturer 142.980s 2555.177us 1 1 100.00
chip_sw_example_concurrency 143.650s 2614.818us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 163.470s 5641.973us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 374.620s 5093.973us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 162.970s 2890.615us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3696.070s 33520.578us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 46.000s 2049.180us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3696.070s 33520.578us 1 1 100.00
chip_csr_rw 374.620s 5093.973us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.140s 39.478us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 272.650s 4422.797us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 272.650s 4422.797us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 272.650s 4422.797us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 340.390s 4660.214us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 340.390s 4660.214us 1 1 100.00
chip_sw_uart_tx_rx_idx1 367.350s 4403.096us 1 1 100.00
chip_sw_uart_tx_rx_idx2 397.300s 5096.837us 1 1 100.00
chip_sw_uart_tx_rx_idx3 333.920s 4410.112us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 357.920s 4677.880us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 283.210s 3694.969us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 709.430s 8526.516us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 159.540s 5776.909us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 159.540s 5776.909us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 134.630s 2691.209us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 159.230s 2941.889us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 180.540s 4560.241us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 477.260s 9035.599us 1 1 100.00
chip_tap_straps_testunlock0 83.000s 2966.813us 1 1 100.00
chip_tap_straps_rma 82.730s 2425.363us 1 1 100.00
chip_tap_straps_prod 1042.160s 17477.824us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 141.010s 3103.136us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 767.070s 9170.850us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 517.790s 6052.975us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 517.790s 6052.975us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 599.000s 8412.280us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 2128.350s 20454.157us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 298.650s 3462.440us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 601.550s 5973.333us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3381.480s 19105.295us 1 1 100.00
chip_sw_aes_enc_jitter_en 132.990s 2790.477us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 753.520s 7301.715us 1 1 100.00
chip_sw_hmac_enc_jitter_en 148.490s 3399.816us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1331.120s 11189.773us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 167.010s 3370.614us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 390.110s 5539.263us 1 1 100.00
chip_sw_clkmgr_jitter 130.960s 2670.383us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 170.490s 3652.177us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 708.510s 8621.063us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 193.030s 5147.334us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 166.960s 3474.955us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 193.030s 5147.334us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 164.620s 2904.646us 1 1 100.00
chip_sw_aes_smoketest 138.620s 3147.160us 1 1 100.00
chip_sw_aon_timer_smoketest 145.240s 2906.142us 1 1 100.00
chip_sw_clkmgr_smoketest 142.480s 2537.291us 1 1 100.00
chip_sw_csrng_smoketest 149.900s 3094.206us 1 1 100.00
chip_sw_entropy_src_smoketest 806.360s 7455.471us 1 1 100.00
chip_sw_gpio_smoketest 147.110s 2876.499us 1 1 100.00
chip_sw_hmac_smoketest 201.130s 3554.250us 1 1 100.00
chip_sw_kmac_smoketest 171.650s 3383.723us 1 1 100.00
chip_sw_otbn_smoketest 1028.660s 9154.082us 1 1 100.00
chip_sw_pwrmgr_smoketest 221.930s 5800.266us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 269.090s 5887.086us 1 1 100.00
chip_sw_rv_plic_smoketest 125.630s 2795.916us 1 1 100.00
chip_sw_rv_timer_smoketest 157.610s 3376.234us 1 1 100.00
chip_sw_rstmgr_smoketest 119.540s 2455.680us 1 1 100.00
chip_sw_sram_ctrl_smoketest 87.710s 2859.084us 1 1 100.00
chip_sw_uart_smoketest 93.380s 2310.891us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 163.620s 3209.757us 1 1 100.00
chip_sw_rom_functests 1 1 100.00
rom_keymgr_functest 340.450s 5998.812us 1 1 100.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7737.010s 61885.620us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2519.150s 15059.836us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 609.340s 16021.775us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 201.530s 3139.880us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 226.150s 3523.588us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6922.930s 53924.465us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7007.190s 57927.045us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
chip_tl_errors 105.880s 3710.917us 1 1 100.00
tl_d_illegal_access 1 1 100.00
chip_tl_errors 105.880s 3710.917us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3696.070s 33520.578us 1 1 100.00
chip_same_csr_outstanding 2475.250s 30752.749us 1 1 100.00
chip_csr_hw_reset 163.470s 5641.973us 1 1 100.00
chip_csr_rw 374.620s 5093.973us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3696.070s 33520.578us 1 1 100.00
chip_same_csr_outstanding 2475.250s 30752.749us 1 1 100.00
chip_csr_hw_reset 163.470s 5641.973us 1 1 100.00
chip_csr_rw 374.620s 5093.973us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 19.360s 883.358us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.470s 35.435us 1 1 100.00
xbar_smoke_large_delays 54.050s 8988.031us 1 1 100.00
xbar_smoke_slow_rsp 41.330s 4838.849us 1 1 100.00
xbar_random_zero_delays 12.360s 198.307us 1 1 100.00
xbar_random_large_delays 299.910s 50177.898us 1 1 100.00
xbar_random_slow_rsp 261.420s 31149.356us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 7.460s 219.708us 1 1 100.00
xbar_error_and_unmapped_addr 13.260s 545.168us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 6.700s 149.844us 1 1 100.00
xbar_error_and_unmapped_addr 13.260s 545.168us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 24.470s 497.657us 1 1 100.00
xbar_access_same_device_slow_rsp 25.470s 2710.779us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 41.740s 2559.718us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 151.090s 2890.502us 1 1 100.00
xbar_stress_all_with_error 93.110s 4462.569us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 339.020s 7096.094us 1 1 100.00
xbar_stress_all_with_reset_error 77.710s 517.566us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2519.150s 15059.836us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2273.810s 31141.795us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2486.960s 16920.049us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2048.300s 12063.799us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2455.930s 15944.694us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2607.010s 16779.818us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2398.350s 15910.022us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2377.470s 14824.352us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 27.580s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 27.150s 10.300us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 28.660s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 24.850s 10.320us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 19.530s 10.320us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 17.410s 10.220us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 24.620s 10.380us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 17.220s 10.340us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 17.210s 10.140us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 17.570s 10.360us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.030s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 17.250s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.080s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 16.840s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 20.270s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.680s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 18.870s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 17.970s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 16.930s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.890s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 27.160s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 20.730s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 18.380s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 16.790s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 16.300s 10.360us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 1895.400s 13077.451us 1 1 100.00
rom_e2e_asm_init_dev 2499.680s 15900.630us 1 1 100.00
rom_e2e_asm_init_prod 2476.270s 15333.676us 1 1 100.00
rom_e2e_asm_init_prod_end 2415.650s 15425.589us 1 1 100.00
rom_e2e_asm_init_rma 2322.340s 14799.823us 1 1 100.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 4037.550s 28885.975us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 2245.210s 15788.634us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 4203.740s 30618.152us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2456.110s 15975.099us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3151.110s 35135.257us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3151.110s 35135.257us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 119.150s 2467.827us 1 1 100.00
chip_sw_aes_enc_jitter_en 132.990s 2790.477us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 164.190s 2488.852us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 176.560s 3096.740us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1362.420s 11031.881us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 125.270s 2532.099us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 256.680s 4404.488us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 362.990s 4516.779us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 500.410s 5552.635us 1 1 100.00
chip_plic_all_irqs_10 259.840s 3558.991us 1 1 100.00
chip_plic_all_irqs_20 360.990s 4547.387us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 164.000s 3847.937us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 863.760s 11894.472us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 306.770s 4920.517us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 93.450s 3034.026us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 849.610s 6817.925us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 962.640s 7519.525us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 766.290s 7775.555us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8598.990s 255704.375us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 231.390s 3750.849us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 221.930s 5800.266us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 231.390s 3750.849us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 311.890s 7837.485us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 311.890s 7837.485us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 282.320s 7583.727us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 351.120s 5391.340us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 591.420s 5973.893us 1 1 100.00
chip_sw_aes_idle 176.560s 3096.740us 1 1 100.00
chip_sw_hmac_enc_idle 163.330s 3287.433us 1 1 100.00
chip_sw_kmac_idle 161.720s 3561.808us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 309.080s 4395.589us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 219.940s 4303.776us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 307.790s 4409.652us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 285.890s 4456.554us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 667.240s 8491.627us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 367.430s 4154.651us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 427.500s 5628.220us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 373.340s 4662.233us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 360.060s 4549.492us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 347.980s 4444.805us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 371.660s 5302.230us 1 1 100.00
chip_sw_ast_clk_outputs 599.000s 8412.280us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 483.410s 11589.661us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 373.340s 4662.233us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 360.060s 4549.492us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 298.650s 3462.440us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 601.550s 5973.333us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3381.480s 19105.295us 1 1 100.00
chip_sw_aes_enc_jitter_en 132.990s 2790.477us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 753.520s 7301.715us 1 1 100.00
chip_sw_hmac_enc_jitter_en 148.490s 3399.816us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1331.120s 11189.773us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 167.010s 3370.614us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 390.110s 5539.263us 1 1 100.00
chip_sw_clkmgr_jitter 130.960s 2670.383us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 140.720s 2901.982us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 307.230s 4236.808us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 605.900s 6580.715us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3013.700s 24164.486us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 172.760s 3383.458us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 139.730s 3122.934us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 916.140s 10794.336us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 185.850s 3292.040us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 263.840s 4531.667us 1 1 100.00
chip_sw_flash_init_reduced_freq 1212.480s 21835.065us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2777.950s 25903.874us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 599.000s 8412.280us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 396.840s 5035.404us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 232.160s 3202.301us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 362.990s 4516.779us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 849.610s 6817.925us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1002.570s 7461.866us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 128.490s 2673.271us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 389.300s 6753.715us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 150.260s 2896.933us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2945.540s 18083.130us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 155.590s 2524.264us 1 1 100.00
chip_sw_edn_entropy_reqs 603.530s 5994.440us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 155.590s 2524.264us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1002.570s 7461.866us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 161.060s 2957.056us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1308.250s 18724.970us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 649.350s 5739.830us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 601.550s 5973.333us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 340.880s 3928.750us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 298.650s 3462.440us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3219.600s 44127.147us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1308.250s 18724.970us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 204.420s 3380.434us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 908.160s 8536.020us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 221.300s 4047.968us 1 1 100.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3219.600s 44127.147us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 221.300s 4047.968us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 221.300s 4047.968us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_wr_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 221.300s 4047.968us 1 1 100.00
chip_sw_flash_lc_seed_hw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 221.300s 4047.968us 1 1 100.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 362.990s 4516.779us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 133.630s 6664.321us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 520.420s 5576.139us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 410.980s 5041.431us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 410.980s 5041.431us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 121.600s 3308.433us 1 1 100.00
chip_sw_hmac_enc_jitter_en 148.490s 3399.816us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 163.330s 3287.433us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1590.660s 11025.286us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 652.290s 5867.657us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 336.100s 3996.254us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 370.110s 5292.315us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 382.350s 5185.659us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 307.770s 3755.367us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 908.160s 8536.020us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1331.120s 11189.773us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1050.500s 8980.823us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1362.420s 11031.881us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2707.730s 15970.542us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 163.790s 3092.057us 1 1 100.00
chip_sw_kmac_mode_kmac 199.930s 3099.775us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 167.010s 3370.614us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 908.160s 8536.020us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 538.100s 10193.496us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 160.570s 3418.345us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1263.430s 9548.091us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 161.720s 3561.808us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 256.680s 4404.488us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 477.260s 9035.599us 1 1 100.00
chip_tap_straps_rma 82.730s 2425.363us 1 1 100.00
chip_tap_straps_prod 1042.160s 17477.824us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 153.120s 3347.817us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 538.100s 10193.496us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 538.100s 10193.496us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 538.100s 10193.496us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1073.560s 10279.392us 1 1 100.00
chip_sw_lc_ctrl_broadcast 21 22 95.45
chip_prim_tl_access 133.630s 6664.321us 1 1 100.00
chip_rv_dm_lc_disabled 306.040s 13336.044us 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 221.300s 4047.968us 1 1 100.00
chip_sw_flash_rma_unlocked 3219.600s 44127.147us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 173.280s 2984.751us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 408.030s 6439.668us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 419.110s 6261.497us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 511.270s 7291.651us 0 1 0.00
chip_sw_lc_ctrl_transition 538.100s 10193.496us 1 1 100.00
chip_sw_keymgr_key_derivation 908.160s 8536.020us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 364.060s 8644.616us 1 1 100.00
chip_sw_sram_ctrl_execution_main 436.600s 7875.005us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 483.410s 11589.661us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 367.430s 4154.651us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 427.500s 5628.220us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 373.340s 4662.233us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 360.060s 4549.492us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 347.980s 4444.805us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 371.660s 5302.230us 1 1 100.00
chip_tap_straps_dev 477.260s 9035.599us 1 1 100.00
chip_tap_straps_rma 82.730s 2425.363us 1 1 100.00
chip_tap_straps_prod 1042.160s 17477.824us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 142.070s 3656.936us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 82.290s 3694.523us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 82.980s 3168.326us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 77.720s 3414.324us 1 1 100.00
chip_lc_test_locked 2 2 100.00
chip_rv_dm_lc_disabled 306.040s 13336.044us 1 1 100.00
chip_sw_lc_walkthrough_testunlocks 1494.940s 31417.125us 1 1 100.00
chip_sw_lc_walkthrough 5 5 100.00
chip_sw_lc_walkthrough_dev 4020.710s 49095.117us 1 1 100.00
chip_sw_lc_walkthrough_prod 4193.140s 52111.233us 1 1 100.00
chip_sw_lc_walkthrough_prodend 476.380s 10744.364us 1 1 100.00
chip_sw_lc_walkthrough_rma 3625.040s 46027.202us 1 1 100.00
chip_sw_lc_walkthrough_testunlocks 1494.940s 31417.125us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 81.640s 2753.744us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 63.420s 2570.561us 1 1 100.00
rom_volatile_raw_unlock 71.740s 2862.691us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3162.710s 17438.394us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3381.480s 19105.295us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 591.420s 5973.893us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 591.420s 5973.893us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 591.420s 5973.893us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 281.800s 4180.247us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 538.100s 10193.496us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1308.250s 18724.970us 1 1 100.00
chip_sw_otbn_mem_scramble 281.800s 4180.247us 1 1 100.00
chip_sw_keymgr_key_derivation 908.160s 8536.020us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 466.380s 5824.845us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 148.140s 3058.566us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1308.250s 18724.970us 1 1 100.00
chip_sw_otbn_mem_scramble 281.800s 4180.247us 1 1 100.00
chip_sw_keymgr_key_derivation 908.160s 8536.020us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 466.380s 5824.845us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 148.140s 3058.566us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 538.100s 10193.496us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 335.410s 4667.107us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 153.120s 3347.817us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 133.630s 6664.321us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 173.280s 2984.751us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 408.030s 6439.668us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 419.110s 6261.497us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 511.270s 7291.651us 0 1 0.00
chip_sw_lc_ctrl_transition 538.100s 10193.496us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 133.630s 6664.321us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 717.400s 6500.972us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 292.680s 6793.967us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1019.750s 23062.307us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 269.030s 7784.611us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 289.360s 7584.228us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 217.660s 4905.169us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1137.530s 22167.241us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 382.420s 9893.194us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 311.890s 7837.485us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 667.620s 9762.032us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 272.990s 4517.718us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 292.680s 6793.967us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 197.370s 3398.780us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 216.820s 5841.310us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 207.700s 5796.708us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 296.100s 5330.080us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1482.350s 20866.511us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 695.150s 8009.521us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1013.070s 12555.386us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1575.470s 28958.766us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 153.260s 2354.434us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 362.990s 4516.779us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 364.060s 8644.616us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 364.060s 8644.616us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 1013.070s 12555.386us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1482.350s 20866.511us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 272.990s 4517.718us 1 1 100.00
chip_sw_pwrmgr_smoketest 221.930s 5800.266us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 182.640s 3596.770us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 170.350s 3370.429us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 276.910s 4617.072us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 863.760s 11894.472us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 149.550s 3038.524us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 362.990s 4516.779us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 962.640s 7519.525us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 459.920s 4656.142us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 479.630s 5474.013us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 156.160s 3261.757us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 148.140s 3058.566us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 170.350s 3370.429us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 170.350s 3370.429us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 750.680s 11913.380us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 893.570s 13097.072us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 182.640s 3596.770us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 198.690s 2961.303us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 338.390s 6960.831us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 82.730s 2425.363us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 306.040s 13336.044us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 500.410s 5552.635us 1 1 100.00
chip_plic_all_irqs_10 259.840s 3558.991us 1 1 100.00
chip_plic_all_irqs_20 360.990s 4547.387us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 118.810s 2507.400us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 151.660s 3538.477us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2519.150s 15059.836us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 409.530s 6647.620us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 187.690s 2948.607us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 208.130s 3591.959us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 172.560s 3321.850us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 466.380s 5824.845us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 390.110s 5539.263us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 400.760s 7977.861us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 430.040s 7703.092us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 436.600s 7875.005us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 362.990s 4516.779us 1 1 100.00
chip_sw_data_integrity_escalation 517.790s 6052.975us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 695.150s 8009.521us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1141.770s 22937.296us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 140.120s 2583.728us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 181.410s 3379.163us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 329.080s 4809.220us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1141.770s 22937.296us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1141.770s 22937.296us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2533.420s 20844.702us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2533.420s 20844.702us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 290.830s 6026.452us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3151.110s 35135.257us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 109.020s 2882.420us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 163.820s 3253.543us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 273.580s 3992.352us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 315.000s 3881.150us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1052.610s 7774.995us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4657.620s 31237.299us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1874.240s 11677.479us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 140.250s 2442.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 158.660s 2877.091us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 123.560s 2798.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 8862.960s 72249.639us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1018.840s 6158.427us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 147.350s 3460.882us 0 1 0.00
rom_e2e_jtag_debug_dev 168.270s 4859.488us 0 1 0.00
rom_e2e_jtag_debug_rma 323.140s 4719.339us 0 1 0.00
rom_e2e_jtag_inject 2 3 66.67
rom_e2e_jtag_inject_test_unlocked0 48.740s 2157.274us 0 1 0.00
rom_e2e_jtag_inject_dev 159.860s 3398.457us 1 1 100.00
rom_e2e_jtag_inject_rma 205.970s 4190.688us 1 1 100.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 9.634s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 1 1 100.00
chip_sw_clkmgr_jitter_frequency 493.830s 5367.593us 1 1 100.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 314.640s 3138.248us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 745.330s 5965.557us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 668.510s 6131.112us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 200.030s 2698.750us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 563.680s 4396.137us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 66.430s 2464.529us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 133.980s 3192.204us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 190.650s 5377.085us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 252.120s 4403.599us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1013.070s 12555.386us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 147.350s 3460.882us 0 1 0.00
rom_e2e_jtag_debug_dev 168.270s 4859.488us 0 1 0.00
rom_e2e_jtag_debug_rma 323.140s 4719.339us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 304.610s 5618.954us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 362.990s 4516.779us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5547.020s 38936.212us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5547.020s 38936.212us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 175.410s 3565.691us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 340.390s 4660.214us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3071.070s 19667.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 141.470s 2871.655us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 308.910s 5441.279us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 64.510s 2358.273us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 121.210s 3330.011us 1 1 100.00
chip_sw_otp_ctrl_descrambling 156.010s 2910.632us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 210.400s 4166.048us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.890s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 176.440s 3593.278us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32543) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 96809110045031538346429704076708326857343524227212694889239384175107626931776 221
UVM_ERROR @ 2049.179657 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32543) { a_addr: 'h104e4 a_data: 'hceac5894 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h19980 d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2049.179657 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 46212482134051522168534146986421172352974703160504581491768827799632191263447 397
UVM_ERROR @ 2948.606516 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 2948.606516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 95152605317373725502412446272308152533437737150646434018732454290450549827264 421
UVM_ERROR @ 7291.651224 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7291.651224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 86373101251180796184685822263180588567898175335255815861869815750451441499131 403
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3192.204344 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3192.204344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 2128379606841992743823629737580436634183840434634705033132580806509102892236 394
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2673.270824 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2673.270824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
chip_sw_otp_ctrl_rot_auth_config 13031410250389857809546848032872756718231532580438368335018218818147650968746 425
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 66531752121935836885659277527674467298972824878691529858547334350667409240697 409
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 32792917310454353224926553631618595427331674096526407618575489010417128317283 454
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 21338268246159749772110727136333353016718093925278797086635213456220866258062 466
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 23892176732287627690770110223476349992673741777726030576724924385859344971194 433
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@77925) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 100149054332316033268774182339761828255172273183202978897303585921289657183101 426
UVM_ERROR @ 3370.428673 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@77925) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3370.428673 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 34168022724729164649953618271222353302323043157900663923381098581156530873099 409
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 9893.194000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9893.194000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 86215582394367298699228688646587320083138747509169338418610101513895605459711 408
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7584.228000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7584.228000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 113028960487857972483912544788853125587357317547231014095634535899935567255915 399
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 5841.310000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5841.310000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 103791660895648085042349207922997804976831426898591657735800929053020689996396 400
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 7837.485000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7837.485000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 19742326390791013055765387985551254616049576377319292930431831294761581904469 413
UVM_ERROR @ 35135.256647 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 35135.256647 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:367)] CHECK-fail: Expect alert *!
chip_sw_alert_test 115357321558619890134323988376484455379461317918230878627866087387155213219782 390
UVM_ERROR @ 2532.098584 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:367)] CHECK-fail: Expect alert 55!
UVM_INFO @ 2532.098584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 69326914337649981141827946788403907711513415230992769198119144622383825944251 391
UVM_ERROR @ 3034.025924 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3034.025924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 22596183903922124738202347211695549528398695969226967529397467456552853737316 None
Job timed out after 240 minutes
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 49602690692481323763574939529253834715723644721963681678200191077102978028522 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.642s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 37558877403207477513612048846017404280246660130915392613784938183226825968559 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.188s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 49654122215572515361674322238656594493661343856025486574274986398330513594280 402
UVM_ERROR @ 3139.880000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3139.880000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 87353216283639126393248221247419544940477157970800059699469077420780661945908 396
UVM_ERROR @ 3523.588000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3523.588000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
chip_sw_ast_clk_rst_inputs 29836017983362615756636029820221733156040176088420601069164085048049671660311 415
UVM_ERROR @ 20454.156612 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 20454.156612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 68791154365595599780499409103811601471750301578798866347789009543571660964463 500
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 42062550500926928578652414162489191335805131254316995300937336789811495914210 497
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 27148993397877604869409195978658781144066760603147837013648180348007560577458 503
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 93715920567952173614064607370410147890538627194354660584536556858613676771277 503
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 24234335227784908139213605178994765949969880856310674372990023538919363462323 476
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 94380268791012690724560599660682915046732025266694825264134402200126782907765 478
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 61336590889354962318398782320807740566324387593541103379246635141617434482675 474
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 44240577139390296389210950285079295850343705542265700818367975909287615435745 512
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 66595223912798899475140648944420492764855184822176738152206527625612880086427 503
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 45022606316515234739718258588639287850973890947391426341648659416665525925202 531
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 101725312287971891874382279168854242480131754659758219284829406596867063610366 566
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 108888752835230191557921546743743490712809537920642767811087060620722686895708 583
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 26077854694185178295070901117741030418300004183911071054896951358559584249808 590
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 111173377256244615141378420581275054918706569728471053293509252843964175778504 535
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 108984924087455461815336302094896243884358165677287642249999448259311341845238 495
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 26848937078607303235134590958291953468842196269739090149866977326401633118518 495
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 103141876076037109508157158901174685300394187123164897357665180202713723327880 561
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 36969626317118557381312131178320116139244411326564371891684921235151904353443 499
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 32308992886922885674631187759642280668821940741221190942650894683592917994824 548
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 7917664250487478660846714603266400313743855743312655003045213421170021959390 510
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 67235938576043588775035662933820346822686691153773349964864485143766085189061 492
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 92980320530188930275049494864522780421931583168716564254197363517965094796199 477
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 67813694995025872483622924976881240414217789539867218738344904294175947382957 452
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 85674570066859566972961581215970158440505265857239300311690382379895668509574 466
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 25974473965303999703400145226365864583054816989185671021925908613186508213059 478
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds
rom_e2e_jtag_debug_dev 40408852471255120235584069458749794185197604414910213740332881943912412482062 440
UVM_ERROR @ 4859.488194 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
UVM_INFO @ 4859.488194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_no_meas 53245784967793186928881477638912290319248338371286007194302439419689038711741 416
UVM_ERROR @ 15788.633766 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 15788.633766 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
rom_raw_unlock 24316116578602418036053594889473471852575571203351105066472790729999385616314 440
UVM_FATAL @ 16021.774545 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
UVM_INFO @ 16021.774545 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---