Simulation Results: clkmgr

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.58 %
  • code
  • 98.24 %
  • assert
  • 94.07 %
  • func
  • 85.42 %
  • line
  • 98.96 %
  • branch
  • 98.65 %
  • cond
  • 94.55 %
  • toggle
  • 99.03 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
85.71%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.790s 45.852us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.090s 257.804us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.700s 49.204us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 2.730s 220.551us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.420s 139.213us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.950s 62.494us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.700s 49.204us 1 1 100.00
clkmgr_csr_aliasing 1.420s 139.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.720s 22.424us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.750s 24.921us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.730s 24.398us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.690s 75.158us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.790s 45.852us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.280s 230.767us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 4.020s 1859.997us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.280s 230.767us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 2.630s 745.816us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.700s 18.315us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 0.930s 36.032us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 0.930s 36.032us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.090s 257.804us 1 1 100.00
clkmgr_csr_rw 0.700s 49.204us 1 1 100.00
clkmgr_csr_aliasing 1.420s 139.213us 1 1 100.00
clkmgr_same_csr_outstanding 0.880s 86.020us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.090s 257.804us 1 1 100.00
clkmgr_csr_rw 0.700s 49.204us 1 1 100.00
clkmgr_csr_aliasing 1.420s 139.213us 1 1 100.00
clkmgr_same_csr_outstanding 0.880s 86.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.320s 210.067us 0 1 0.00
clkmgr_tl_intg_err 1.290s 70.980us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 4.200s 1930.186us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 4.200s 1930.186us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 4.200s 1930.186us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 4.200s 1930.186us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.930s 553.312us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.290s 70.980us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.280s 230.767us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 4.020s 1859.997us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 4.200s 1930.186us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.760s 53.014us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.710s 36.202us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.800s 64.586us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.730s 46.011us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.730s 45.142us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.700s 49.204us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.320s 210.067us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.700s 49.204us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.700s 49.204us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.320s 210.067us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.420s 706.927us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 22.830s 4124.502us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 103788758226085307749530428433819013166115747064110895226236095674962246306677 156
UVM_ERROR @ 210067426 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 210067426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---