| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
~~~~~~~~~~~~~~~^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/util/reggen/gen_fpv.py", line 46, in gen_fpv
with open(reg_top_path, 'w', encoding='UTF-8') as fout:
~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: './edn_csr_assert_fpv.sv'
Error: CSR assert gen failed:
Command '['/nightly/current_run/opentitan/util/regtool.py', '-f', '-t', '.', '/nightly/current_run/opentitan/hw/ip/edn/data/edn.hjson']' returned non-zero exit status 1.
ERROR: "/nightly/current_run/.venv/bin/python3 /nightly/current_run/opentitan/hw/formal/tools/csr_assert_gen/csr_assert_gen.py /nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_sva-csr_assert_gen_0.1-3d387bb0e518b1118852a68f330120acb02137bd0daf464c8d791c909b9efe25/csr_assert_gen_input.yml" exited with an error code. See stderr for details.
ERROR: Setup failed : Failed to run generator 'csr_assert_gen'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| Error-[CFCILFBI] Cannot find cell in liblist | ||||
| cover_reg_top | None | 1714 |
Error-[CFCILFBI] Cannot find cell in liblist
src/lowrisc_dv_edn_sva_0.1/edn_bind.sv, 16
Cell 'edn_csr_assert_fpv' cannot be found in liblist for binding instance
'tb.dut.edn_csr_assert'.
Liblist: work
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_smoke | 45394261044178895399886644743936022345653504350316233912079774380893490621310 | None | ||
| edn_regwen | 77620703242999047749753268770623385927922321781886912151628635717092029134990 | None | ||
| edn_genbits | 9805152506173500078838073816974385249268492890888923168649252101836953743993 | None | ||
| edn_stress_all | 23783088965206835281066629398952333779596542216829457812333990860499365917437 | None | ||
| edn_stress_all_with_rand_reset | 95278549248397701865268388206817921838355751297169626697170679673077184005475 | None | ||
| edn_intr | 93380914487530291656924582984503717376618821377364151382329096106970206807572 | None | ||
| edn_alert | 62916726379765387204853331867809423128112052009735615723035319392119411166762 | None | ||
| edn_err | 23339351855658372477252039962335335639415627829210256089531832116781507561577 | None | ||
| edn_disable | 59623919434159988347136114581176816078015556404997403890972519512642831734275 | None | ||
| edn_disable_auto_req_mode | 12407214223764682730200602577742260723204218703181407640978748412515478629096 | None | ||
| edn_sec_cm | 79914983445551662287483710304191179460676882763413443778478041665735335960556 | None | ||
| edn_alert_test | 28967417760437218798846743884521037764956063315152612407615745982346091495900 | None | ||
| edn_tl_errors | 69005831639445298171884747239579419980323109490835953631500676479964304817408 | None | ||
| edn_tl_intg_err | 22429532994530520941694689228651331166838263888336677462645692122575437786525 | None | ||
| edn_intr_test | 95405690570032459440443189462474225803831118495121589452516390567508025183758 | None | ||
| edn_csr_hw_reset | 112517246645402446464677735554250059882372293000197950979030849444681190898498 | None | ||
| edn_csr_rw | 107107497749374358344827438384020154922452748810552455146407028615326503265745 | None | ||
| edn_csr_bit_bash | 83811875498175388882380433941782978943973548793206969232664292064904424132930 | None | ||
| edn_csr_aliasing | 60117701407242234027035446391024177683444043196840626325577008372170451061638 | None | ||
| edn_same_csr_outstanding | 62798245442039350218384937836989665823068503273346943233440036179379019492813 | None | ||
| edn_csr_mem_rw_with_rand_reset | 888063991755015224671667095577973413840002635725927893755514370585782554954 | None | ||
| edn | None | None | ||
| edn | None | None | ||