| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Error-[CFCILFBI] Cannot find cell in liblist | ||||
| default | None | 1714 |
Error-[CFCILFBI] Cannot find cell in liblist
src/lowrisc_dv_edn_sva_0.1/edn_bind.sv, 16
Cell 'edn_csr_assert_fpv' cannot be found in liblist for binding instance
'tb.dut.edn_csr_assert'.
Liblist: work
|
|
| Job returned non-zero exit code | ||||
| cover_reg_top | None | None |
File "/nightly/current_run/opentitan/util/reggen/gen_fpv.py", line 46, in gen_fpv
with open(reg_top_path, 'w', encoding='UTF-8') as fout:
~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: './edn_csr_assert_fpv.sv'
Error: CSR assert gen failed:
Command '['/nightly/current_run/opentitan/util/regtool.py', '-f', '-t', '.', '/nightly/current_run/opentitan/hw/ip/edn/data/edn.hjson']' returned non-zero exit status 1.
ERROR: "/nightly/current_run/.venv/bin/python3 /nightly/current_run/opentitan/hw/formal/tools/csr_assert_gen/csr_assert_gen.py /nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/generator_cache/lowrisc_dv_edn_sva-csr_assert_gen_0.1-3d387bb0e518b1118852a68f330120acb02137bd0daf464c8d791c909b9efe25/csr_assert_gen_input.yml" exited with an error code. See stderr for details.
ERROR: Setup failed : Failed to run generator 'csr_assert_gen'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
INFO: Generating lowrisc:dv:edn_env-ral:0.1
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_tl_errors | 57663161881806322216335340335960951449679607779001414600684786549403217364660 | None | ||
| edn_tl_intg_err | 73094756875243636303769582062111645674481905334036340959125983719262091966498 | None | ||
| edn_intr_test | 11821423943135869027224405093553449840688306067299770102810355833577095396198 | None | ||
| edn_csr_hw_reset | 43993782772276401478598448869608317778165349742183664389827216591427355181864 | None | ||
| edn_csr_rw | 102155908901144661504096136527238654444214360344974082401974489449713357214649 | None | ||
| edn_csr_bit_bash | 66106494986650809001195483337779375735097184323437790956111285558774912349144 | None | ||
| edn_csr_aliasing | 63450004957425230908115703631661181839135494328687017114452377041899022201577 | None | ||
| edn_same_csr_outstanding | 41973200377984785850671956739622985506215730502851569075767644759262283238876 | None | ||
| edn_csr_mem_rw_with_rand_reset | 20797541676083459679401271952689654835796793490879987975729798458378666557158 | None | ||
| edn_smoke | 47494237605856108892289769994377630604220825585861830583666973641376634294599 | None | ||
| edn_regwen | 55055148255219010143113271442639174437871100176534099440662503088888738439691 | None | ||
| edn_genbits | 77965874531676830967938683785347620619638426103732429437621700629435504045878 | None | ||
| edn_stress_all | 69314749245347767357747737324812836979756500073011661069015076536716934592858 | None | ||
| edn_stress_all_with_rand_reset | 69350167494262211911606071069459205299709388257542570225715853663088862259461 | None | ||
| edn_intr | 105305955073502831121927571460529841332925733975956790155203319360387827372438 | None | ||
| edn_alert | 34510104632765984651682893542958196965418237076665618587202912169565478948091 | None | ||
| edn_err | 17611930101026002008116054521832335433709040038745039880803927517028681634707 | None | ||
| edn_disable | 58328668239493349859615801119513777315064349512277816417317399431142581889784 | None | ||
| edn_disable_auto_req_mode | 44890394342342922407336069682791555332844097712461782092542161358251826868766 | None | ||
| edn_sec_cm | 12494729440540498649624429723834815729894857373018192309821395791018732951002 | None | ||
| edn_alert_test | 13498109548852042614898328600699638422788016799289785356935527659215821469224 | None | ||
| edn | None | None | ||
| edn | None | None | ||