| V1 |
|
100.00% |
| V2 |
|
92.59% |
| V2S |
|
95.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| entropy_src_smoke | 3.000s | 32.756us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 18.400us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| entropy_src_csr_rw | 1.000s | 19.388us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| entropy_src_csr_bit_bash | 6.000s | 358.585us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| entropy_src_csr_aliasing | 2.000s | 46.194us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| entropy_src_csr_mem_rw_with_rand_reset | 2.000s | 28.823us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| entropy_src_csr_rw | 1.000s | 19.388us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 46.194us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 2 | 3 | 66.67 | |||
| entropy_src_smoke | 3.000s | 32.756us | 1 | 1 | 100.00 | |
| entropy_src_rng | 77.000s | 11135.324us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 151.000s | 8848.370us | 0 | 1 | 0.00 | |
| firmware_mode | 0 | 1 | 0.00 | |||
| entropy_src_fw_ov | 151.000s | 8848.370us | 0 | 1 | 0.00 | |
| rng_mode | 1 | 1 | 100.00 | |||
| entropy_src_rng | 77.000s | 11135.324us | 1 | 1 | 100.00 | |
| rng_max_rate | 1 | 1 | 100.00 | |||
| entropy_src_rng_max_rate | 133.000s | 17078.467us | 1 | 1 | 100.00 | |
| health_checks | 1 | 1 | 100.00 | |||
| entropy_src_rng | 77.000s | 11135.324us | 1 | 1 | 100.00 | |
| conditioning | 1 | 1 | 100.00 | |||
| entropy_src_rng | 77.000s | 11135.324us | 1 | 1 | 100.00 | |
| interrupts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 77.000s | 11135.324us | 1 | 1 | 100.00 | |
| entropy_src_intr | 9.000s | 1110.921us | 1 | 1 | 100.00 | |
| alerts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 77.000s | 11135.324us | 1 | 1 | 100.00 | |
| entropy_src_functional_alerts | 6.000s | 175.601us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| entropy_src_stress_all | 330.000s | 20341.538us | 1 | 1 | 100.00 | |
| functional_errors | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 252.395us | 1 | 1 | 100.00 | |
| firmware_ov_read_contiguous_data | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov_contiguous | 3.000s | 33.823us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| entropy_src_intr_test | 2.000s | 13.703us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| entropy_src_alert_test | 3.000s | 42.688us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 4.000s | 96.414us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 4.000s | 96.414us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 18.400us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 1.000s | 19.388us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 46.194us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 2.000s | 196.811us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 18.400us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 1.000s | 19.388us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 46.194us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 2.000s | 196.811us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| entropy_src_tl_intg_err | 4.000s | 123.932us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 155.508us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 2 | 2 | 100.00 | |||
| entropy_src_rng | 77.000s | 11135.324us | 1 | 1 | 100.00 | |
| entropy_src_cfg_regwen | 2.000s | 15.370us | 1 | 1 | 100.00 | |
| sec_cm_config_mubi | 1 | 1 | 100.00 | |||
| entropy_src_rng | 77.000s | 11135.324us | 1 | 1 | 100.00 | |
| sec_cm_config_redun | 1 | 1 | 100.00 | |||
| entropy_src_rng | 77.000s | 11135.324us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 2 | 50.00 | |||
| entropy_src_rng | 77.000s | 11135.324us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 151.000s | 8848.370us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 252.395us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 155.508us | 1 | 1 | 100.00 | |
| sec_cm_ack_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 252.395us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 155.508us | 1 | 1 | 100.00 | |
| sec_cm_rng_bkgn_chk | 1 | 1 | 100.00 | |||
| entropy_src_rng | 77.000s | 11135.324us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 252.395us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 155.508us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 252.395us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 155.508us | 1 | 1 | 100.00 | |
| sec_cm_ctr_local_esc | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 252.395us | 1 | 1 | 100.00 | |
| sec_cm_esfinal_rdata_bus_consistency | 1 | 1 | 100.00 | |||
| entropy_src_functional_alerts | 6.000s | 175.601us | 1 | 1 | 100.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| entropy_src_tl_intg_err | 4.000s | 123.932us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| external_health_tests | 1 | 1 | 100.00 | |||
| entropy_src_rng_with_xht_rsps | 42.000s | 10058.968us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* | ||||
| entropy_src_fw_ov | 64092176006935634822169755771289879409923102880049999249756481266059286222711 | 1194 |
UVM_ERROR @ 8848370186 ps: (cip_base_scoreboard.sv:354) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:4
UVM_INFO @ 8848370186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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