| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
97.73% |
| V3 |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 74.560s | 218.908us | 1 | 1 | 100.00 | |
| smoke_hw | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke_hw | 14.180s | 17.778us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 12.240s | 35.923us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 7.110s | 52.706us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_bit_bash | 19.720s | 706.034us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_aliasing | 42.830s | 460.621us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_mem_rw_with_rand_reset | 10.750s | 74.754us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| flash_ctrl_csr_rw | 7.110s | 52.706us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 42.830s | 460.621us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_walk | 6.060s | 17.482us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_partial_access | 6.500s | 59.241us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sw_op | 1 | 1 | 100.00 | |||
| flash_ctrl_sw_op | 9.720s | 114.804us | 1 | 1 | 100.00 | |
| host_read_direct | 1 | 1 | 100.00 | |||
| flash_ctrl_host_dir_rd | 23.710s | 68.740us | 1 | 1 | 100.00 | |
| rma_hw_if | 3 | 3 | 100.00 | |||
| flash_ctrl_hw_rma | 1513.760s | 340404.153us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_rma_reset | 500.310s | 80141.707us | 1 | 1 | 100.00 | |
| flash_ctrl_lcmgr_intg | 6.390s | 22.113us | 1 | 1 | 100.00 | |
| host_controller_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_host_ctrl_arb | 1169.020s | 660735.603us | 1 | 1 | 100.00 | |
| erase_suspend | 1 | 1 | 100.00 | |||
| flash_ctrl_erase_suspend | 103.300s | 367.138us | 1 | 1 | 100.00 | |
| program_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_prog_reset | 8.440s | 21.196us | 1 | 1 | 100.00 | |
| full_memory_access | 1 | 1 | 100.00 | |||
| flash_ctrl_full_mem_access | 2095.440s | 312999.607us | 1 | 1 | 100.00 | |
| rd_buff_eviction | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_buff_evict | 78.420s | 2798.230us | 1 | 1 | 100.00 | |
| rd_buff_eviction_w_ecc | 3 | 3 | 100.00 | |||
| flash_ctrl_rw_evict | 14.040s | 60.177us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_evict_all_en | 14.410s | 28.352us | 1 | 1 | 100.00 | |
| flash_ctrl_re_evict | 13.480s | 127.401us | 1 | 1 | 100.00 | |
| host_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 159.910s | 3506.336us | 1 | 1 | 100.00 | |
| host_interleave | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 159.910s | 3506.336us | 1 | 1 | 100.00 | |
| memory_protection | 1 | 1 | 100.00 | |||
| flash_ctrl_mp_regions | 220.060s | 10853.845us | 1 | 1 | 100.00 | |
| fetch_code | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 16.620s | 1902.099us | 1 | 1 | 100.00 | |
| all_partitions | 1 | 1 | 100.00 | |||
| flash_ctrl_rand_ops | 101.450s | 2367.224us | 1 | 1 | 100.00 | |
| error_mp | 1 | 1 | 100.00 | |||
| flash_ctrl_error_mp | 369.680s | 2393.474us | 1 | 1 | 100.00 | |
| error_prog_win | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_win | 295.070s | 1445.806us | 1 | 1 | 100.00 | |
| error_prog_type | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_type | 905.460s | 1631.822us | 1 | 1 | 100.00 | |
| error_read_seed | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_read_seed_err | 5.380s | 22.837us | 1 | 1 | 100.00 | |
| read_write_overflow | 1 | 1 | 100.00 | |||
| flash_ctrl_oversize_error | 121.580s | 1403.998us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 17.580s | 34.185us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 1 | 1 | 100.00 | |||
| flash_ctrl_connect | 7.950s | 29.152us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| flash_ctrl_stress_all | 161.610s | 472.837us | 1 | 1 | 100.00 | |
| secret_partition | 2 | 2 | 100.00 | |||
| flash_ctrl_hw_sec_otp | 54.940s | 2611.643us | 1 | 1 | 100.00 | |
| flash_ctrl_otp_reset | 51.240s | 73.394us | 1 | 1 | 100.00 | |
| isolation_partition | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1513.760s | 340404.153us | 1 | 1 | 100.00 | |
| interrupts | 4 | 4 | 100.00 | |||
| flash_ctrl_intr_rd | 97.770s | 2646.261us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr | 54.440s | 12014.622us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_rd_slow_flash | 106.190s | 33973.227us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr_slow_flash | 143.710s | 25245.247us | 1 | 1 | 100.00 | |
| invalid_op | 1 | 1 | 100.00 | |||
| flash_ctrl_invalid_op | 37.210s | 1513.475us | 1 | 1 | 100.00 | |
| mid_op_rst | 1 | 1 | 100.00 | |||
| flash_ctrl_mid_op_rst | 59.590s | 673.784us | 1 | 1 | 100.00 | |
| double_bit_err | 5 | 5 | 100.00 | |||
| flash_ctrl_read_word_sweep_derr | 19.950s | 24.476us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_derr | 116.120s | 7739.402us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 136.650s | 4394.288us | 1 | 1 | 100.00 | |
| flash_ctrl_derr_detect | 88.130s | 1171.811us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 417.390s | 13947.413us | 1 | 1 | 100.00 | |
| single_bit_err | 3 | 3 | 100.00 | |||
| flash_ctrl_read_word_sweep_serr | 9.750s | 87.221us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_serr | 83.160s | 3497.146us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_serr | 145.880s | 1934.841us | 1 | 1 | 100.00 | |
| singlebit_err_counter | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_counter | 55.140s | 9714.401us | 1 | 1 | 100.00 | |
| singlebit_err_address | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_address | 63.320s | 7288.651us | 1 | 1 | 100.00 | |
| scramble | 5 | 5 | 100.00 | |||
| flash_ctrl_wo | 122.800s | 8961.261us | 1 | 1 | 100.00 | |
| flash_ctrl_write_word_sweep | 8.300s | 59.586us | 1 | 1 | 100.00 | |
| flash_ctrl_read_word_sweep | 6.330s | 105.636us | 1 | 1 | 100.00 | |
| flash_ctrl_ro | 69.620s | 492.249us | 1 | 1 | 100.00 | |
| flash_ctrl_rw | 317.220s | 3613.609us | 1 | 1 | 100.00 | |
| filesystem_support | 1 | 1 | 100.00 | |||
| flash_ctrl_fs_sup | 22.470s | 1781.763us | 1 | 1 | 100.00 | |
| rma_write_process_error | 2 | 2 | 100.00 | |||
| flash_ctrl_rma_err | 592.470s | 83106.023us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_prog_rma_wipe_err | 46.780s | 10056.510us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| flash_ctrl_alert_test | 6.450s | 35.724us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| flash_ctrl_intr_test | 5.210s | 55.994us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 7.670s | 40.539us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 7.670s | 40.539us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 12.240s | 35.923us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 7.110s | 52.706us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 42.830s | 460.621us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 9.270s | 172.715us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 12.240s | 35.923us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 7.110s | 52.706us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 42.830s | 460.621us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 9.270s | 172.715us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 51.220s | 80.027us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 51.220s | 80.027us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 51.220s | 80.027us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 51.220s | 80.027us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors_with_csr_rw | 14.300s | 556.637us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| flash_ctrl_tl_intg_err | 186.720s | 747.183us | 1 | 1 | 100.00 | |
| flash_ctrl_sec_cm | 1535.190s | 18655.031us | 1 | 1 | 100.00 | |
| sec_cm_reg_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 186.720s | 747.183us | 1 | 1 | 100.00 | |
| sec_cm_host_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 186.720s | 747.183us | 1 | 1 | 100.00 | |
| sec_cm_mem_bus_integrity | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 14.040s | 230.272us | 1 | 1 | 100.00 | |
| flash_ctrl_wr_intg | 6.440s | 159.977us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 74.560s | 218.908us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 4 | 4 | 100.00 | |||
| flash_ctrl_otp_reset | 51.240s | 73.394us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 17.580s | 34.185us | 1 | 1 | 100.00 | |
| flash_ctrl_sec_info_access | 47.050s | 4450.324us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 7.950s | 29.152us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_config_regwen | 7.500s | 66.290us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 7.110s | 52.706us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 51.220s | 80.027us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 7.110s | 52.706us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 51.220s | 80.027us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 7.110s | 52.706us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 51.220s | 80.027us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_global_esc | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 17.580s | 34.185us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_local_esc | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 14.040s | 230.272us | 1 | 1 | 100.00 | |
| flash_ctrl_access_after_disable | 7.810s | 131.398us | 1 | 1 | 100.00 | |
| sec_cm_mem_addr_infection | 1 | 1 | 100.00 | |||
| flash_ctrl_host_addr_infection | 12.180s | 64.961us | 1 | 1 | 100.00 | |
| sec_cm_mem_disable_config_mubi | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 17.580s | 34.185us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 16.620s | 1902.099us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| flash_ctrl_rw | 317.220s | 3613.609us | 1 | 1 | 100.00 | |
| sec_cm_mem_integrity | 3 | 3 | 100.00 | |||
| flash_ctrl_rw_serr | 145.880s | 1934.841us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 136.650s | 4394.288us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 417.390s | 13947.413us | 1 | 1 | 100.00 | |
| sec_cm_rma_entry_mem_sec_wipe | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1513.760s | 340404.153us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1535.190s | 18655.031us | 1 | 1 | 100.00 | |
| sec_cm_phy_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1535.190s | 18655.031us | 1 | 1 | 100.00 | |
| sec_cm_phy_prog_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1535.190s | 18655.031us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1535.190s | 18655.031us | 1 | 1 | 100.00 | |
| sec_cm_phy_arbiter_ctrl_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb_redun | 13.230s | 860.082us | 1 | 1 | 100.00 | |
| sec_cm_phy_host_grant_ctrl_consistency | 0 | 1 | 0.00 | |||
| flash_ctrl_phy_host_grant_err | 6.060s | 13.749us | 0 | 1 | 0.00 | |
| sec_cm_phy_ack_ctrl_consistency | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_ack_consistency | 7.590s | 548.351us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1535.190s | 18655.031us | 1 | 1 | 100.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1535.190s | 18655.031us | 1 | 1 | 100.00 | |
| sec_cm_prog_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1535.190s | 18655.031us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| asymmetric_read_path | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_ooo | 16.510s | 27.002us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| flash_ctrl_basic_rw | 87.620s | 906.763us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' | ||||
| flash_ctrl_phy_host_grant_err | 45062001861997256058615982903795939436506459773443818341744512863507166890879 | 122 |
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
UVM_ERROR @ 13748.7 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 13748.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|