Simulation Results: hmac

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.89 %
  • code
  • 97.78 %
  • assert
  • 96.42 %
  • func
  • 42.46 %
  • line
  • 99.74 %
  • branch
  • 99.01 %
  • cond
  • 96.01 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.720s 2557.651us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.670s 52.430us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.640s 212.040us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.160s 697.960us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.120s 311.250us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.970s 124.675us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.640s 212.040us 1 1 100.00
hmac_csr_aliasing 2.120s 311.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 50.470s 5195.897us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 53.080s 2438.349us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 185.450s 24626.111us 1 1 100.00
hmac_test_sha384_vectors 18.490s 800.593us 1 1 100.00
hmac_test_sha512_vectors 18.400s 218.261us 1 1 100.00
hmac_test_hmac256_vectors 6.270s 215.037us 1 1 100.00
hmac_test_hmac384_vectors 8.560s 314.034us 1 1 100.00
hmac_test_hmac512_vectors 7.320s 2407.419us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 1.450s 351.775us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 158.020s 2488.212us 1 1 100.00
error 1 1 100.00
hmac_error 38.210s 3368.868us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 51.340s 3731.711us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.720s 2557.651us 1 1 100.00
hmac_long_msg 50.470s 5195.897us 1 1 100.00
hmac_back_pressure 53.080s 2438.349us 1 1 100.00
hmac_datapath_stress 158.020s 2488.212us 1 1 100.00
hmac_burst_wr 1.450s 351.775us 1 1 100.00
hmac_stress_all 250.640s 23588.890us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.720s 2557.651us 1 1 100.00
hmac_long_msg 50.470s 5195.897us 1 1 100.00
hmac_back_pressure 53.080s 2438.349us 1 1 100.00
hmac_datapath_stress 158.020s 2488.212us 1 1 100.00
hmac_wipe_secret 51.340s 3731.711us 1 1 100.00
hmac_test_sha256_vectors 185.450s 24626.111us 1 1 100.00
hmac_test_sha384_vectors 18.490s 800.593us 1 1 100.00
hmac_test_sha512_vectors 18.400s 218.261us 1 1 100.00
hmac_test_hmac256_vectors 6.270s 215.037us 1 1 100.00
hmac_test_hmac384_vectors 8.560s 314.034us 1 1 100.00
hmac_test_hmac512_vectors 7.320s 2407.419us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.720s 2557.651us 1 1 100.00
hmac_long_msg 50.470s 5195.897us 1 1 100.00
hmac_back_pressure 53.080s 2438.349us 1 1 100.00
hmac_datapath_stress 158.020s 2488.212us 1 1 100.00
hmac_burst_wr 1.450s 351.775us 1 1 100.00
hmac_error 38.210s 3368.868us 1 1 100.00
hmac_wipe_secret 51.340s 3731.711us 1 1 100.00
hmac_test_sha256_vectors 185.450s 24626.111us 1 1 100.00
hmac_test_sha384_vectors 18.490s 800.593us 1 1 100.00
hmac_test_sha512_vectors 18.400s 218.261us 1 1 100.00
hmac_test_hmac256_vectors 6.270s 215.037us 1 1 100.00
hmac_test_hmac384_vectors 8.560s 314.034us 1 1 100.00
hmac_test_hmac512_vectors 7.320s 2407.419us 1 1 100.00
hmac_stress_all 250.640s 23588.890us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 250.640s 23588.890us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.550s 45.423us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.580s 46.184us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.180s 61.019us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.180s 61.019us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.670s 52.430us 1 1 100.00
hmac_csr_rw 0.640s 212.040us 1 1 100.00
hmac_csr_aliasing 2.120s 311.250us 1 1 100.00
hmac_same_csr_outstanding 1.350s 64.052us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.670s 52.430us 1 1 100.00
hmac_csr_rw 0.640s 212.040us 1 1 100.00
hmac_csr_aliasing 2.120s 311.250us 1 1 100.00
hmac_same_csr_outstanding 1.350s 64.052us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.810s 333.824us 1 1 100.00
hmac_tl_intg_err 2.660s 569.833us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.660s 569.833us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.720s 2557.651us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.510s 320.110us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 22.480s 2148.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 195.127us 1 1 100.00

Error Messages

   Test seed line log context