i2c Simulation Results

Simulation Results: i2c

09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.51 %

code
81.27 %

assert
96.19 %

func
79.07 %

line
96.04 %

branch
91.91 %

cond
85.27 %

toggle
89.66 %

FSM
43.45 %

Validation stages

V1		100.00%
V2		93.88%
V2S		100.00%
V3		0.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	57.790s	7365.745us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	14.200s	6331.479us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.700s	25.612us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.800s	31.898us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.470s	519.820us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.560s	141.957us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.890s	173.158us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.800s	31.898us	1	1	100.00
	i2c_csr_aliasing	1.560s	141.957us	1	1	100.00

46/49 passed

93.88 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.060s	64.354us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	128.540s	14421.245us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	94.290s	5522.098us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.740s	29.434us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	47.200s	13554.576us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	85.550s	2006.417us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.990s	93.084us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.560s	2514.661us	1	1	100.00
	i2c_host_fifo_reset_rx	2.920s	496.347us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	51.380s	11515.496us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	7.530s	1136.539us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	2.520s	355.571us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.860s	3536.474us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	50.740s	53500.301us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.380s	465.125us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	8.270s	2670.282us	1	1	100.00
	i2c_target_intr_smoke	5.980s	5077.510us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.070s	635.789us	1	1	100.00
	i2c_target_fifo_reset_tx	0.780s	632.495us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	30.810s	27471.416us	1	1	100.00
	i2c_target_stress_rd	8.270s	2670.282us	1	1	100.00
	i2c_target_intr_stress_wr	5.610s	5087.555us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	6.230s	1428.499us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	11.060s	3771.444us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.710s	628.325us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.110s	623.345us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.670s	1326.612us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.970s	93.065us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	94.290s	5522.098us	1	1	100.00
	i2c_host_perf_precise	1.350s	79.356us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	7.530s	1136.539us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.060s	64.233us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.170s	3644.234us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.710s	9352.885us	1	1	100.00
	i2c_target_nack_txstretch	1.780s	548.885us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	8.830s	322.194us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.730s	1002.694us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.590s	61.714us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.640s	16.131us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.870s	220.128us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.870s	220.128us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.700s	25.612us	1	1	100.00
	i2c_csr_rw	0.800s	31.898us	1	1	100.00
	i2c_csr_aliasing	1.560s	141.957us	1	1	100.00
	i2c_same_csr_outstanding	0.940s	52.821us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.700s	25.612us	1	1	100.00
	i2c_csr_rw	0.800s	31.898us	1	1	100.00
	i2c_csr_aliasing	1.560s	141.957us	1	1	100.00
	i2c_same_csr_outstanding	0.940s	52.821us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.980s	271.259us	1	1	100.00
	i2c_sec_cm	0.870s	250.535us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.980s	271.259us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	41.560s	1010.578us	1
target_error_intr				1
	i2c_target_unexp_stop	1.360s	441.917us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	3.160s	624.774us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	68641177237827373799532738277712488081207595457967207337675050925393421885475	91	UVM_ERROR @ 64353808 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 64353808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	48089172705925824257375033229324373476051712149500349337696021783911630438448	96	UVM_ERROR @ 14421245219 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 14421245219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	32996540203942617983213694327249490195676719746533386219464576048535913761068	84	UVM_ERROR @ 624774322 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 624774322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	106605077218101582626438861922266488111200745158550644983544859864180842651406	81	UVM_ERROR @ 3536473739 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 3536473739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	113984867123158262966589293083841132604345057388461763600021956798136517004454	75	UVM_ERROR @ 441916526 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 143 [0x8f]) UVM_INFO @ 441916526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	88671372169925681279529272088394658471974586028116263470018481743280474514955	91	UVM_ERROR @ 1010577967 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1010577967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---