Simulation Results: lc_ctrl

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.87 %
  • code
  • 83.51 %
  • assert
  • 94.13 %
  • func
  • 88.97 %
  • line
  • 97.04 %
  • branch
  • 93.51 %
  • cond
  • 78.67 %
  • toggle
  • 75.98 %
  • FSM
  • 72.34 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.510s 24.871us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.780s 16.510us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 17.353us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.930s 42.160us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 35.785us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.100s 94.082us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 17.353us 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 35.785us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.820s 302.566us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.340s 311.124us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.800s 12.431us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.610s 491.152us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 2.780s 15.311us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.710s 1221.582us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 2.780s 15.311us 0 1 0.00
lc_ctrl_prog_failure 2.610s 491.152us 1 1 100.00
lc_ctrl_errors 7.710s 1221.582us 1 1 100.00
lc_ctrl_security_escalation 3.940s 284.575us 1 1 100.00
lc_ctrl_jtag_state_failure 5.230s 1102.033us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.950s 1265.442us 1 1 100.00
lc_ctrl_jtag_errors 24.400s 11065.817us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.250s 95.003us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.150s 137.027us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.370s 678.827us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.760s 257.847us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.970s 103.310us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.740s 103.766us 1 1 100.00
lc_ctrl_jtag_alert_test 1.250s 46.344us 1 1 100.00
lc_ctrl_jtag_smoke 10.640s 786.834us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.130s 399.367us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.950s 1265.442us 1 1 100.00
lc_ctrl_jtag_errors 24.400s 11065.817us 1 1 100.00
lc_ctrl_jtag_access 3.810s 4905.637us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.500s 2694.713us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.080s 79.207us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.020s 27.790us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 13.120s 4317.361us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.980s 111.292us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.010s 122.074us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.010s 122.074us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 16.510us 1 1 100.00
lc_ctrl_csr_rw 1.000s 17.353us 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 35.785us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.040s 50.923us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 16.510us 1 1 100.00
lc_ctrl_csr_rw 1.000s 17.353us 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 35.785us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.040s 50.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.180s 90.008us 1 1 100.00
lc_ctrl_sec_cm 6.230s 901.393us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.180s 90.008us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.340s 311.124us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 2.780s 15.311us 0 1 0.00
lc_ctrl_sec_cm 6.230s 901.393us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 2.780s 15.311us 0 1 0.00
lc_ctrl_sec_cm 6.230s 901.393us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 2.780s 15.311us 0 1 0.00
lc_ctrl_sec_cm 6.230s 901.393us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 2.780s 15.311us 0 1 0.00
lc_ctrl_sec_cm 6.230s 901.393us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 2.780s 15.311us 0 1 0.00
lc_ctrl_sec_cm 6.230s 901.393us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 2.780s 15.311us 0 1 0.00
lc_ctrl_sec_cm 6.230s 901.393us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 2.780s 15.311us 0 1 0.00
lc_ctrl_sec_cm 6.230s 901.393us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 2.780s 15.311us 0 1 0.00
lc_ctrl_sec_cm 6.230s 901.393us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.940s 284.575us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.820s 302.566us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.130s 399.367us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.450s 330.462us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.450s 330.462us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.090s 2382.080us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.300s 1460.482us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.300s 1460.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 11.540s 244.357us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 110579779970730331618875415539552232582762156662806475681628344722974721227489 217
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 15311303 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 15311303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 65041690534330750826407588534046773316262191258502935597801466087599531578547 575
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1102033433 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1102033433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 12421358584961747967944545777307914048537540355002293350384442659904935337991 201
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 4317360549 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 4317360549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108466886946129792335364720649798788426120159144259340403190736641971385779804 1169
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 244356980 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 244356980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---