| V1 |
|
100.00% |
| V2 |
|
87.50% |
| V2S |
|
67.86% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| lc_ctrl_smoke | 3.740s | 372.686us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 1.060s | 16.415us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_rw | 0.760s | 180.956us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_bit_bash | 1.130s | 54.782us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_aliasing | 1.050s | 47.154us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_mem_rw_with_rand_reset | 1.020s | 54.093us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| lc_ctrl_csr_rw | 0.760s | 180.956us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 1.050s | 47.154us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| state_post_trans | 0 | 1 | 0.00 | |||
| lc_ctrl_state_post_trans | 5.290s | 33.150us | 0 | 1 | 0.00 | |
| regwen_during_op | 1 | 1 | 100.00 | |||
| lc_ctrl_regwen_during_op | 6.130s | 363.992us | 1 | 1 | 100.00 | |
| rand_wr_claim_transition_if | 1 | 1 | 100.00 | |||
| lc_ctrl_claim_transition_if | 0.840s | 13.777us | 1 | 1 | 100.00 | |
| lc_prog_failure | 1 | 1 | 100.00 | |||
| lc_ctrl_prog_failure | 1.520s | 90.784us | 1 | 1 | 100.00 | |
| lc_state_failure | 0 | 1 | 0.00 | |||
| lc_ctrl_state_failure | 5.860s | 992.917us | 0 | 1 | 0.00 | |
| lc_errors | 1 | 1 | 100.00 | |||
| lc_ctrl_errors | 6.890s | 3172.627us | 1 | 1 | 100.00 | |
| security_escalation | 5 | 7 | 71.43 | |||
| lc_ctrl_state_failure | 5.860s | 992.917us | 0 | 1 | 0.00 | |
| lc_ctrl_prog_failure | 1.520s | 90.784us | 1 | 1 | 100.00 | |
| lc_ctrl_errors | 6.890s | 3172.627us | 1 | 1 | 100.00 | |
| lc_ctrl_security_escalation | 9.140s | 784.902us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_failure | 4.970s | 1973.752us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_prog_failure | 4.240s | 674.871us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_errors | 27.510s | 1386.927us | 1 | 1 | 100.00 | |
| jtag_access | 13 | 13 | 100.00 | |||
| lc_ctrl_jtag_csr_hw_reset | 1.410s | 76.539us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_rw | 1.260s | 36.657us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_bit_bash | 9.870s | 7210.333us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_aliasing | 7.330s | 852.605us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_same_csr_outstanding | 1.180s | 60.846us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 1.780s | 685.002us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_alert_test | 2.470s | 488.574us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_smoke | 1.620s | 82.877us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_post_trans | 7.760s | 608.316us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_prog_failure | 4.240s | 674.871us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_errors | 27.510s | 1386.927us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_access | 5.490s | 738.080us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_regwen_during_op | 8.270s | 1810.531us | 1 | 1 | 100.00 | |
| jtag_priority | 1 | 1 | 100.00 | |||
| lc_ctrl_jtag_priority | 2.090s | 188.710us | 1 | 1 | 100.00 | |
| lc_ctrl_volatile_unlock | 1 | 1 | 100.00 | |||
| lc_ctrl_volatile_unlock_smoke | 1.090s | 23.336us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all | 5.400s | 60.184us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| lc_ctrl_alert_test | 0.860s | 71.832us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_errors | 1.640s | 126.576us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_errors | 1.640s | 126.576us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 1.060s | 16.415us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_rw | 0.760s | 180.956us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 1.050s | 47.154us | 1 | 1 | 100.00 | |
| lc_ctrl_same_csr_outstanding | 1.260s | 96.839us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 1.060s | 16.415us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_rw | 0.760s | 180.956us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 1.050s | 47.154us | 1 | 1 | 100.00 | |
| lc_ctrl_same_csr_outstanding | 1.260s | 96.839us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| lc_ctrl_tl_intg_err | 1.440s | 230.400us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 6.020s | 463.182us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_intg_err | 1.440s | 230.400us | 1 | 1 | 100.00 | |
| sec_cm_transition_config_regwen | 1 | 1 | 100.00 | |||
| lc_ctrl_regwen_during_op | 6.130s | 363.992us | 1 | 1 | 100.00 | |
| sec_cm_manuf_state_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.860s | 992.917us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.020s | 463.182us | 1 | 1 | 100.00 | |
| sec_cm_transition_ctr_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.860s | 992.917us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.020s | 463.182us | 1 | 1 | 100.00 | |
| sec_cm_manuf_state_bkgn_chk | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.860s | 992.917us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.020s | 463.182us | 1 | 1 | 100.00 | |
| sec_cm_transition_ctr_bkgn_chk | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.860s | 992.917us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.020s | 463.182us | 1 | 1 | 100.00 | |
| sec_cm_state_config_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.860s | 992.917us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.020s | 463.182us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.860s | 992.917us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.020s | 463.182us | 1 | 1 | 100.00 | |
| sec_cm_kmac_fsm_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.860s | 992.917us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.020s | 463.182us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.860s | 992.917us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.020s | 463.182us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| lc_ctrl_security_escalation | 9.140s | 784.902us | 1 | 1 | 100.00 | |
| sec_cm_main_ctrl_flow_consistency | 1 | 2 | 50.00 | |||
| lc_ctrl_state_post_trans | 5.290s | 33.150us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_state_post_trans | 7.760s | 608.316us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_mubi | 7.420s | 1095.252us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_ctrl_mubi | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_mubi | 7.420s | 1095.252us | 1 | 1 | 100.00 | |
| sec_cm_token_digest | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_digest | 5.590s | 406.941us | 1 | 1 | 100.00 | |
| sec_cm_token_mux_ctrl_redun | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_mux | 10.330s | 508.983us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_mux_redun | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_mux | 10.330s | 508.983us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all_with_rand_reset | 7.210s | 517.481us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | ||||
| lc_ctrl_state_failure | 55711159806717569936635629977089153611106431348148548215203582641064831252962 | 1454 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 992917121 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 992917121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| lc_ctrl_state_post_trans | 28164421119579211252118531943347686890444065535714416854119819637081145434054 | 530 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 33150329 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 33150329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| lc_ctrl_jtag_state_failure | 69476528242796050780681059563464925452815045261544115780958997068393049702219 | 733 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1973752247 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1973752247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| lc_ctrl_stress_all | 82524891275833829625788309706459463405389906244104237975953799532278631616126 | 754 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 60184122 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 60184122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| lc_ctrl_stress_all_with_rand_reset | 36204484162062559473700737936732834086635162270345173066445365127197645205558 | 840 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 517481338 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 517481338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|