Simulation Results: otp_ctrl

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.55 %
  • code
  • 78.73 %
  • assert
  • 93.12 %
  • func
  • 72.81 %
  • line
  • 88.33 %
  • branch
  • 83.40 %
  • cond
  • 90.24 %
  • toggle
  • 87.93 %
  • FSM
  • 43.75 %
Validation stages
V1
90.91%
V2
96.00%
V2S
94.64%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.460s 55.386us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.230s 213.381us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.870s 228.833us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.270s 76.290us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.490s 238.410us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.200s 152.100us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.130s 103.847us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.270s 76.290us 1 1 100.00
otp_ctrl_csr_aliasing 2.200s 152.100us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.070s 39.693us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.100s 39.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.390s 313.948us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.000s 153.303us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 8.470s 2211.224us 1 1 100.00
otp_ctrl_check_fail 9.210s 802.078us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.100s 125.311us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 22.630s 11761.392us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 10.360s 623.621us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 7.900s 5367.638us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 44.150s 18611.630us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 7.540s 993.740us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 13.810s 2883.138us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 102.730s 17959.191us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.370s 52.616us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.790s 109.127us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.230s 1329.884us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.230s 1329.884us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.870s 228.833us 1 1 100.00
otp_ctrl_csr_rw 1.270s 76.290us 1 1 100.00
otp_ctrl_csr_aliasing 2.200s 152.100us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.640s 153.058us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.870s 228.833us 1 1 100.00
otp_ctrl_csr_rw 1.270s 76.290us 1 1 100.00
otp_ctrl_csr_aliasing 2.200s 152.100us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.640s 153.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 11.490s 10275.330us 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.490s 10275.330us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.230s 213.381us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.230s 213.381us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
otp_ctrl_macro_errs 7.540s 993.740us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
otp_ctrl_macro_errs 7.540s 993.740us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.140s 351.052us 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.000s 153.303us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 9.210s 802.078us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 22.630s 11761.392us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 22.630s 11761.392us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 22.630s 11761.392us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 22.630s 11761.392us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 22.630s 11761.392us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.230s 213.381us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 22.630s 11761.392us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.230s 213.381us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 110.840s 10457.429us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.100s 125.311us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.230s 213.381us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.230s 213.381us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 7.540s 993.740us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.690s 5996.284us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.530s 73.420us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_csr_mem_rw_with_rand_reset 53538477053555590750889199379495705313267966225203425279298562246633042541086 89
UVM_ERROR @ 103847483 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 103847483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 90544644126371648485382531020436989062683449982431170019953580414350726258605 89
UVM_ERROR @ 73420229 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 73420229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_macro_errs 74978135490827275947403821725028965672215760251832195637728632427895352490718 8139
UVM_ERROR @ 993739578 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2049 [0x801]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 993739578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---