Simulation Results: pattgen

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.78 %
  • code
  • 98.87 %
  • assert
  • 96.04 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 8.000s 649.510us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 13.088us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 13.628us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 212.107us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 35.671us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 79.684us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 13.628us 1 1 100.00
pattgen_csr_aliasing 1.000s 35.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 136.000s 93077.208us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 2.000s 378.107us 1 1 100.00
error 1 1 100.00
pattgen_error 6.000s 47.362us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 2.000s 34.883us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 14.970us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 52.200us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 98.128us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 98.128us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 13.088us 1 1 100.00
pattgen_csr_rw 1.000s 13.628us 1 1 100.00
pattgen_csr_aliasing 1.000s 35.671us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 14.791us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 13.088us 1 1 100.00
pattgen_csr_rw 1.000s 13.628us 1 1 100.00
pattgen_csr_aliasing 1.000s 35.671us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 14.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 1.000s 94.268us 1 1 100.00
pattgen_tl_intg_err 2.000s 89.278us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 89.278us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 24.000s 3357.133us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 28.000s 10054.782us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21)
pattgen_inactive_level 47439054483152323058619799018895010672206554720173326715016666463900852921713 96
UVM_FATAL @ 10054782162 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x7b374c50, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10054782162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 1791922244748833701194212748312617164134690137627019893908622645753811820076 297
UVM_ERROR @ 3345987022 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 3345994430 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3345994430 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/5
UVM_INFO @ 3346088183 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]