pwrmgr Simulation Results

Simulation Results: pwrmgr

09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.69 %

code
94.60 %

assert
96.08 %

func
96.38 %

line
98.92 %

branch
95.42 %

cond
94.63 %

toggle
90.02 %

FSM
94.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		47.06%
V3		50.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	pwrmgr_smoke	0.820s	23.673us	1	1	100.00
csr_hw_reset				1	1	100.00
	pwrmgr_csr_hw_reset	0.660s	46.092us	1	1	100.00
csr_rw				1	1	100.00
	pwrmgr_csr_rw	0.680s	114.439us	1	1	100.00
csr_bit_bash				1	1	100.00
	pwrmgr_csr_bit_bash	2.050s	69.879us	1	1	100.00
csr_aliasing				1	1	100.00
	pwrmgr_csr_aliasing	0.890s	180.671us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	pwrmgr_csr_mem_rw_with_rand_reset	1.080s	49.343us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	pwrmgr_csr_rw	0.680s	114.439us	1	1	100.00
	pwrmgr_csr_aliasing	0.890s	180.671us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wakeup				1	1	100.00
	pwrmgr_wakeup	1.270s	281.463us	1	1	100.00
control_clks				1	1	100.00
	pwrmgr_wakeup	1.270s	281.463us	1	1	100.00
aborted_low_power				2	2	100.00
	pwrmgr_aborted_low_power	0.740s	105.331us	1	1	100.00
	pwrmgr_lowpower_invalid	0.680s	82.908us	1	1	100.00
reset				2	2	100.00
	pwrmgr_reset	0.660s	71.492us	1	1	100.00
	pwrmgr_reset_invalid	1.090s	102.529us	1	1	100.00
main_power_glitch_reset				1	1	100.00
	pwrmgr_reset	0.660s	71.492us	1	1	100.00
reset_wakeup_race				0	1	0.00
	pwrmgr_wakeup_reset	0.890s	1000.000us	0	1	0.00
lowpower_wakeup_race				1	1	100.00
	pwrmgr_lowpower_wakeup_race	1.100s	295.894us	1	1	100.00
disable_rom_integrity_check				1	1	100.00
	pwrmgr_disable_rom_integrity_check	0.670s	81.654us	1	1	100.00
stress_all				1	1	100.00
	pwrmgr_stress_all	1.550s	466.711us	1	1	100.00
intr_test				1	1	100.00
	pwrmgr_intr_test	0.580s	44.052us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	pwrmgr_tl_errors	1.420s	288.713us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	pwrmgr_tl_errors	1.420s	288.713us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	pwrmgr_csr_hw_reset	0.660s	46.092us	1	1	100.00
	pwrmgr_csr_rw	0.680s	114.439us	1	1	100.00
	pwrmgr_csr_aliasing	0.890s	180.671us	1	1	100.00
	pwrmgr_same_csr_outstanding	0.710s	20.063us	1	1	100.00
tl_d_partial_access				4	4	100.00
	pwrmgr_csr_hw_reset	0.660s	46.092us	1	1	100.00
	pwrmgr_csr_rw	0.680s	114.439us	1	1	100.00
	pwrmgr_csr_aliasing	0.890s	180.671us	1	1	100.00
	pwrmgr_same_csr_outstanding	0.710s	20.063us	1	1	100.00

V2S

8/17 passed

47.06 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	2	0.00
	pwrmgr_tl_intg_err	0.600s	9.007us	0	1	0.00
	pwrmgr_sec_cm	0.880s	18.371us	0	1	0.00
prim_count_check				0	1	0.00
	pwrmgr_sec_cm	0.880s	18.371us	0	1	0.00
prim_fsm_check				0	1	0.00
	pwrmgr_sec_cm	0.880s	18.371us	0	1	0.00
sec_cm_bus_integrity				0	1	0.00
	pwrmgr_tl_intg_err	0.600s	9.007us	0	1	0.00
sec_cm_lc_ctrl_intersig_mubi				1	1	100.00
	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	1.540s	1844.170us	1	1	100.00
sec_cm_rom_ctrl_intersig_mubi				0	1	0.00
	pwrmgr_wakeup_reset	0.890s	1000.000us	0	1	0.00
sec_cm_rstmgr_intersig_mubi				1	1	100.00
	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.890s	227.384us	1	1	100.00
sec_cm_esc_rx_clk_bkgn_chk				1	1	100.00
	pwrmgr_esc_clk_rst_malfunc	0.650s	39.696us	1	1	100.00
sec_cm_esc_rx_clk_local_esc				0	1	0.00
	pwrmgr_sec_cm	0.880s	18.371us	0	1	0.00
sec_cm_fsm_sparse				0	1	0.00
	pwrmgr_sec_cm	0.880s	18.371us	0	1	0.00
sec_cm_fsm_terminal				0	1	0.00
	pwrmgr_sec_cm	0.880s	18.371us	0	1	0.00
sec_cm_ctrl_flow_global_esc				1	1	100.00
	pwrmgr_global_esc	0.680s	31.184us	1	1	100.00
sec_cm_main_pd_rst_local_esc				1	1	100.00
	pwrmgr_glitch	0.560s	121.995us	1	1	100.00
sec_cm_ctrl_config_regwen				1	1	100.00
	pwrmgr_sec_cm_ctrl_config_regwen	0.680s	61.815us	1	1	100.00
sec_cm_wakeup_config_regwen				1	1	100.00
	pwrmgr_csr_rw	0.680s	114.439us	1	1	100.00
sec_cm_reset_config_regwen				1	1	100.00
	pwrmgr_csr_rw	0.680s	114.439us	1	1	100.00

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
escalation_timeout				0	1	0.00
	pwrmgr_escalation_timeout	0.680s	531.302us	0	1	0.00
stress_all_with_rand_reset				1	1	100.00
	pwrmgr_stress_all_with_rand_reset	11.350s	4390.120us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
	pwrmgr_tl_intg_err	107581453451930545034143016869642255820426520460470899276813006296611566461197	82	UVM_ERROR @ 9007099 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 9007099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	pwrmgr_sec_cm	109284125096277063185573318609353894869072579020438140023271375010349057967280	76	UVM_ERROR @ 18371231 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 18371231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	pwrmgr_wakeup_reset	61638303332107230709298096890212581538178289816099209986842399048758588093620	191	UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
	pwrmgr_escalation_timeout	16551610128266642036644352348439659147636035376454636183887151836398674478070	72	UVM_ERROR @ 531302344 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A UVM_INFO @ 531302344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---