Simulation Results: rom_ctrl

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.70 %
  • code
  • 98.20 %
  • assert
  • 95.34 %
  • func
  • 93.56 %
  • line
  • 99.46 %
  • branch
  • 98.18 %
  • cond
  • 93.76 %
  • toggle
  • 99.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.080s 696.093us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.570s 221.149us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.580s 484.029us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.970s 553.478us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 128.743us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.040s 478.231us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.580s 484.029us 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 128.743us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.300s 384.842us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.440s 556.271us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.450s 301.141us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 16.380s 594.801us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.890s 4184.824us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.130s 385.134us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.440s 558.658us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.440s 558.658us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.570s 221.149us 1 1 100.00
rom_ctrl_csr_rw 3.580s 484.029us 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 128.743us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.790s 2035.567us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.570s 221.149us 1 1 100.00
rom_ctrl_csr_rw 3.580s 484.029us 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 128.743us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.790s 2035.567us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.910s 6069.445us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.380s 2125.625us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 192.830s 894.344us 0 1 0.00
rom_ctrl_tl_intg_err 23.120s 219.801us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 192.830s 894.344us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 192.830s 894.344us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.910s 6069.445us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.910s 6069.445us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.910s 6069.445us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.910s 6069.445us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.910s 6069.445us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 192.830s 894.344us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 192.830s 894.344us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.080s 696.093us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.080s 696.093us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.080s 696.093us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.120s 219.801us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.910s 6069.445us 1 1 100.00
rom_ctrl_kmac_err_chk 6.890s 4184.824us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.910s 6069.445us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.910s 6069.445us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.910s 6069.445us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.380s 2125.625us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 192.830s 894.344us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 96.930s 3543.845us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 52045166279613777715053833079970157367609486358773391041118110518481992788658 999
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 130773107ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 130773107ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 130773107ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))