Simulation Results: rom_ctrl

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.57 %
  • code
  • 95.56 %
  • assert
  • 95.20 %
  • func
  • 95.94 %
  • line
  • 99.32 %
  • branch
  • 98.18 %
  • cond
  • 94.50 %
  • toggle
  • 99.13 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.230s 230.603us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 12.310s 716.851us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.850s 370.341us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.200s 297.940us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 8.370s 1030.670us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.260s 396.148us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.850s 370.341us 1 1 100.00
rom_ctrl_csr_aliasing 8.370s 1030.670us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.460s 216.830us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 8.320s 299.650us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.170s 231.312us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 20.930s 2182.208us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.800s 3346.485us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.930s 545.105us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.640s 535.928us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.640s 535.928us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.310s 716.851us 1 1 100.00
rom_ctrl_csr_rw 5.850s 370.341us 1 1 100.00
rom_ctrl_csr_aliasing 8.370s 1030.670us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.020s 525.974us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.310s 716.851us 1 1 100.00
rom_ctrl_csr_rw 5.850s 370.341us 1 1 100.00
rom_ctrl_csr_aliasing 8.370s 1030.670us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.020s 525.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.500s 7201.722us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 35.380s 4138.636us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 460.610s 1173.613us 0 1 0.00
rom_ctrl_tl_intg_err 98.960s 621.446us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 460.610s 1173.613us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 460.610s 1173.613us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.500s 7201.722us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.500s 7201.722us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.500s 7201.722us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.500s 7201.722us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.500s 7201.722us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 460.610s 1173.613us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 460.610s 1173.613us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.230s 230.603us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.230s 230.603us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.230s 230.603us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 98.960s 621.446us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.500s 7201.722us 1 1 100.00
rom_ctrl_kmac_err_chk 13.800s 3346.485us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.500s 7201.722us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.500s 7201.722us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.500s 7201.722us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 35.380s 4138.636us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 460.610s 1173.613us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 126.080s 2739.352us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
rom_ctrl_sec_cm 83522201913920701184013978252947631659641225382132904299112957230733300662091 171
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 13297799ps failed at 13297799ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 13307799ps failed at 13307799ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'