Simulation Results: rstmgr

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.00 %
  • code
  • 99.26 %
  • assert
  • 97.72 %
  • func
  • 97.01 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.54 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.180s 229.457us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.920s 98.787us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.720s 86.706us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 6.900s 2271.802us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.050s 90.277us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.920s 128.322us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.720s 86.706us 1 1 100.00
rstmgr_csr_aliasing 1.050s 90.277us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.780s 113.734us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.510s 355.165us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.220s 272.830us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.100s 935.742us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.100s 935.742us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.100s 935.742us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.100s 935.742us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 3.570s 1045.741us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.690s 65.660us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.080s 385.125us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.080s 385.125us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.920s 98.787us 1 1 100.00
rstmgr_csr_rw 0.720s 86.706us 1 1 100.00
rstmgr_csr_aliasing 1.050s 90.277us 1 1 100.00
rstmgr_same_csr_outstanding 1.200s 219.235us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.920s 98.787us 1 1 100.00
rstmgr_csr_rw 0.720s 86.706us 1 1 100.00
rstmgr_csr_aliasing 1.050s 90.277us 1 1 100.00
rstmgr_same_csr_outstanding 1.200s 219.235us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 22.570s 16794.287us 1 1 100.00
rstmgr_tl_intg_err 2.390s 939.663us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 22.570s 16794.287us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 22.570s 16794.287us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.390s 939.663us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.020s 151.065us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.300s 1268.632us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.960s 302.325us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 22.570s 16794.287us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.720s 86.706us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.720s 86.706us 1 1 100.00

Error Messages

   Test seed line log context