Simulation Results: spi_device

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.82 %
  • code
  • 94.08 %
  • assert
  • 94.27 %
  • func
  • 78.12 %
  • line
  • 99.11 %
  • branch
  • 98.35 %
  • cond
  • 95.85 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 57.310s 18666.011us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.180s 151.476us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.880s 367.432us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 16.190s 1527.999us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 9.660s 813.120us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.510s 130.459us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.880s 367.432us 1 1 100.00
spi_device_csr_aliasing 9.660s 813.120us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.860s 38.087us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.440s 24.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.730s 17.130us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.000s 106.516us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.710s 32.299us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.880s 1012.172us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.880s 1012.172us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.920s 1191.635us 1 1 100.00
spi_device_tpm_sts_read 1.010s 24.808us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 34.540s 41450.724us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 10.470s 5102.037us 1 1 100.00
spi_device_flash_all 57.150s 5714.404us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 11.610s 27587.986us 1 1 100.00
spi_device_flash_all 57.150s 5714.404us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 11.610s 27587.986us 1 1 100.00
spi_device_flash_all 57.150s 5714.404us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 57.150s 5714.404us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 11.910s 2036.019us 1 1 100.00
spi_device_flash_all 57.150s 5714.404us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 11.910s 2036.019us 1 1 100.00
spi_device_flash_all 57.150s 5714.404us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 11.910s 2036.019us 1 1 100.00
spi_device_flash_all 57.150s 5714.404us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 11.910s 2036.019us 1 1 100.00
spi_device_flash_all 57.150s 5714.404us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 11.910s 2036.019us 1 1 100.00
spi_device_flash_all 57.150s 5714.404us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.470s 749.019us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 7.570s 634.230us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 7.570s 634.230us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 7.570s 634.230us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.230s 178.649us 1 1 100.00
spi_device_read_buffer_direct 7.150s 2832.049us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 7.570s 634.230us 1 1 100.00
spi_device_flash_all 57.150s 5714.404us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 57.150s 5714.404us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 57.150s 5714.404us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.200s 238.906us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.200s 238.906us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 57.310s 18666.011us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 222.450s 130014.122us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 369.670s 62047.088us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.980s 128.125us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.970s 166.291us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.390s 66.524us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.390s 66.524us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.180s 151.476us 1 1 100.00
spi_device_csr_rw 1.880s 367.432us 1 1 100.00
spi_device_csr_aliasing 9.660s 813.120us 1 1 100.00
spi_device_same_csr_outstanding 2.300s 107.350us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.180s 151.476us 1 1 100.00
spi_device_csr_rw 1.880s 367.432us 1 1 100.00
spi_device_csr_aliasing 9.660s 813.120us 1 1 100.00
spi_device_same_csr_outstanding 2.300s 107.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 9.350s 1962.896us 1 1 100.00
spi_device_sec_cm 1.500s 124.556us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.350s 1962.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 266.140s 840615.908us 1 1 100.00

Error Messages

   Test seed line log context