Simulation Results: sram_ctrl

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.94 %
  • code
  • 91.57 %
  • assert
  • 95.83 %
  • func
  • 94.43 %
  • line
  • 98.12 %
  • branch
  • 95.79 %
  • cond
  • 92.53 %
  • toggle
  • 90.47 %
  • FSM
  • 80.95 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.450s 2809.886us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.720s 17.162us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.790s 11.478us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.250s 97.682us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.040s 52.282us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.540s 1852.227us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.790s 11.478us 1 1 100.00
sram_ctrl_csr_aliasing 1.040s 52.282us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 176.940s 3943.979us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 56.230s 2770.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 533.000s 126626.828us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 142.700s 3540.766us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 854.810s 18122.230us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 674.910s 70324.990us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 50.900s 129418.193us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 856.570s 485698.803us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.590s 465.804us 1 1 100.00
sram_ctrl_partial_access_b2b 262.180s 38273.653us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 16.630s 1692.317us 1 1 100.00
sram_ctrl_throughput_w_partial_write 34.250s 778.329us 1 1 100.00
sram_ctrl_throughput_w_readback 5.380s 723.705us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 418.750s 63212.011us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.370s 1403.899us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 3457.550s 3166864.746us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.830s 30.967us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.520s 558.723us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.520s 558.723us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.720s 17.162us 1 1 100.00
sram_ctrl_csr_rw 0.790s 11.478us 1 1 100.00
sram_ctrl_csr_aliasing 1.040s 52.282us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 51.227us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.720s 17.162us 1 1 100.00
sram_ctrl_csr_rw 0.790s 11.478us 1 1 100.00
sram_ctrl_csr_aliasing 1.040s 52.282us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 51.227us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 27.540s 14132.620us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.690s 39.227us 0 1 0.00
sram_ctrl_tl_intg_err 2.190s 151.542us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.690s 39.227us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.190s 151.542us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 418.750s 63212.011us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 418.750s 63212.011us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.790s 11.478us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 856.570s 485698.803us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 856.570s 485698.803us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 856.570s 485698.803us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 50.900s 129418.193us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.910s 3345.730us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 27.540s 14132.620us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.830s 6605.916us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.450s 2809.886us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.450s 2809.886us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 856.570s 485698.803us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.690s 39.227us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 50.900s 129418.193us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.690s 39.227us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.690s 39.227us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.450s 2809.886us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.690s 39.227us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 58.780s 3948.267us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 71543459916676944424816840132866595004529470052020947828116998436865600894896 98
UVM_ERROR @ 39227376 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 39227376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---