Simulation Results: sysrst_ctrl

 
09/12/2025 17:14:15 sha: 42dbfeb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.80 %
  • code
  • 94.44 %
  • assert
  • 95.79 %
  • func
  • 61.18 %
  • line
  • 98.14 %
  • branch
  • 98.03 %
  • cond
  • 95.28 %
  • toggle
  • 100.00 %
  • FSM
  • 80.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.960s 2111.037us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.360s 2449.653us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.230s 2429.019us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 7.000s 2510.664us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.940s 6074.085us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.560s 2056.348us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 17.510s 39055.319us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.000s 3424.756us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 3.620s 2051.547us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.560s 2056.348us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.000s 3424.756us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 96.010s 57906.394us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 52.900s 102069.428us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 421.950s 237318.006us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.780s 4564.727us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.160s 2514.749us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.850s 2229.055us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 4.020s 3127.599us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.410s 2608.045us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 3.470s 3453.423us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 17.970s 40622.820us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 24.940s 10702.518us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 6.500s 2022.349us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.290s 2007.661us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.090s 2124.241us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.090s 2124.241us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.940s 6074.085us 1 1 100.00
sysrst_ctrl_csr_rw 4.560s 2056.348us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.000s 3424.756us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.950s 8518.868us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.940s 6074.085us 1 1 100.00
sysrst_ctrl_csr_rw 4.560s 2056.348us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.000s 3424.756us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.950s 8518.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_tl_intg_err 21.380s 22235.895us 1 1 100.00
sysrst_ctrl_sec_cm 78.690s 42013.487us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 21.380s 22235.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.710s 6549.073us 1 1 100.00

Error Messages

   Test seed line log context