| V1 |
|
100.00% |
| V2 |
|
97.06% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| uart_smoke | 1.020s | 762.700us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| uart_csr_hw_reset | 0.560s | 19.253us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| uart_csr_rw | 0.620s | 15.763us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| uart_csr_bit_bash | 1.180s | 135.688us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| uart_csr_aliasing | 0.720s | 33.042us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| uart_csr_mem_rw_with_rand_reset | 0.800s | 18.332us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| uart_csr_rw | 0.620s | 15.763us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 0.720s | 33.042us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| base_random_seq | 1 | 1 | 100.00 | |||
| uart_tx_rx | 31.180s | 58715.112us | 1 | 1 | 100.00 | |
| parity | 2 | 2 | 100.00 | |||
| uart_smoke | 1.020s | 762.700us | 1 | 1 | 100.00 | |
| uart_tx_rx | 31.180s | 58715.112us | 1 | 1 | 100.00 | |
| parity_error | 2 | 2 | 100.00 | |||
| uart_intr | 3.750s | 12131.590us | 1 | 1 | 100.00 | |
| uart_rx_parity_err | 54.490s | 70216.646us | 1 | 1 | 100.00 | |
| watermark | 2 | 2 | 100.00 | |||
| uart_tx_rx | 31.180s | 58715.112us | 1 | 1 | 100.00 | |
| uart_intr | 3.750s | 12131.590us | 1 | 1 | 100.00 | |
| fifo_full | 1 | 1 | 100.00 | |||
| uart_fifo_full | 168.290s | 174524.541us | 1 | 1 | 100.00 | |
| fifo_overflow | 1 | 1 | 100.00 | |||
| uart_fifo_overflow | 12.880s | 47727.638us | 1 | 1 | 100.00 | |
| fifo_reset | 1 | 1 | 100.00 | |||
| uart_fifo_reset | 14.690s | 41389.224us | 1 | 1 | 100.00 | |
| rx_frame_err | 1 | 1 | 100.00 | |||
| uart_intr | 3.750s | 12131.590us | 1 | 1 | 100.00 | |
| rx_break_err | 1 | 1 | 100.00 | |||
| uart_intr | 3.750s | 12131.590us | 1 | 1 | 100.00 | |
| rx_timeout | 1 | 1 | 100.00 | |||
| uart_intr | 3.750s | 12131.590us | 1 | 1 | 100.00 | |
| perf | 1 | 1 | 100.00 | |||
| uart_perf | 93.000s | 14932.715us | 1 | 1 | 100.00 | |
| sys_loopback | 1 | 1 | 100.00 | |||
| uart_loopback | 3.280s | 6559.869us | 1 | 1 | 100.00 | |
| line_loopback | 1 | 1 | 100.00 | |||
| uart_loopback | 3.280s | 6559.869us | 1 | 1 | 100.00 | |
| rx_noise_filter | 1 | 1 | 100.00 | |||
| uart_noise_filter | 12.340s | 11296.155us | 1 | 1 | 100.00 | |
| rx_start_bit_filter | 1 | 1 | 100.00 | |||
| uart_rx_start_bit_filter | 5.640s | 4950.252us | 1 | 1 | 100.00 | |
| tx_overide | 1 | 1 | 100.00 | |||
| uart_tx_ovrd | 2.380s | 1149.633us | 1 | 1 | 100.00 | |
| rx_oversample | 1 | 1 | 100.00 | |||
| uart_rx_oversample | 6.940s | 2115.944us | 1 | 1 | 100.00 | |
| long_b2b_transfer | 1 | 1 | 100.00 | |||
| uart_long_xfer_wo_dly | 198.230s | 48746.442us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| uart_stress_all | 5.770s | 5332.956us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| uart_alert_test | 0.590s | 20.842us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| uart_intr_test | 0.590s | 143.589us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| uart_tl_errors | 1.080s | 24.562us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| uart_tl_errors | 1.080s | 24.562us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| uart_csr_hw_reset | 0.560s | 19.253us | 1 | 1 | 100.00 | |
| uart_csr_rw | 0.620s | 15.763us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 0.720s | 33.042us | 1 | 1 | 100.00 | |
| uart_same_csr_outstanding | 0.630s | 17.495us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| uart_csr_hw_reset | 0.560s | 19.253us | 1 | 1 | 100.00 | |
| uart_csr_rw | 0.620s | 15.763us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 0.720s | 33.042us | 1 | 1 | 100.00 | |
| uart_same_csr_outstanding | 0.630s | 17.495us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| uart_sec_cm | 0.750s | 180.646us | 1 | 1 | 100.00 | |
| uart_tl_intg_err | 1.160s | 275.566us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| uart_tl_intg_err | 1.160s | 275.566us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| uart_stress_all_with_rand_reset | 12.680s | 2417.847us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr | ||||
| uart_stress_all | 92368766107364953148328051811899613946257714673841603314977900410908988091255 | 75 |
UVM_ERROR @ 4655788340 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 4655788340 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 4655788340 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 4750489287 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 4750489287 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
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|