Simulation Results: adc_ctrl

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.71 %
  • code
  • 97.01 %
  • assert
  • 95.79 %
  • func
  • 46.34 %
  • line
  • 99.05 %
  • branch
  • 98.64 %
  • cond
  • 95.49 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 11.370s 5785.899us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.010s 621.017us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.940s 447.109us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 118.900s 52563.234us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.650s 1268.428us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.090s 906.924us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.940s 447.109us 1 1 100.00
adc_ctrl_csr_aliasing 2.650s 1268.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 134.960s 334551.267us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 278.090s 336234.963us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 564.770s 328569.838us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 262.790s 159332.244us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 191.240s 193053.322us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 604.580s 392942.032us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 112.020s 341773.960us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 570.870s 339413.195us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 5.080s 3176.564us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 19.200s 24605.982us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 56.010s 116016.749us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 187.660s 229894.434us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.780s 290.099us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.990s 346.060us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.840s 361.570us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.840s 361.570us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.010s 621.017us 1 1 100.00
adc_ctrl_csr_rw 0.940s 447.109us 1 1 100.00
adc_ctrl_csr_aliasing 2.650s 1268.428us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.110s 3908.931us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.010s 621.017us 1 1 100.00
adc_ctrl_csr_rw 0.940s 447.109us 1 1 100.00
adc_ctrl_csr_aliasing 2.650s 1268.428us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.110s 3908.931us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_tl_intg_err 4.380s 4146.675us 1 1 100.00
adc_ctrl_sec_cm 7.810s 7737.422us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 4.380s 4146.675us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 13.690s 17608.874us 1 1 100.00

Error Messages

   Test seed line log context