Simulation Results: alert_handler

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.91 %
  • code
  • 92.16 %
  • assert
  • 97.86 %
  • func
  • 76.71 %
  • line
  • 99.66 %
  • branch
  • 99.73 %
  • cond
  • 93.98 %
  • toggle
  • 93.24 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 2.290s 74.659us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.450s 703.104us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.850s 523.075us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 69.580s 3269.297us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 156.150s 8696.601us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.910s 351.431us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.850s 523.075us 1 1 100.00
alert_handler_csr_aliasing 156.150s 8696.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 36.720s 1057.175us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 12.900s 203.159us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 437.880s 6814.559us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 8.200s 107.733us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 2.290s 74.659us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 19.830s 2279.712us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 12.000s 298.680us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 2.580s 111.145us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 623.480s 12468.753us 1 1 100.00
alert_handler_lpg_stub_clk 752.250s 22195.051us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 767.650s 15521.820us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 18.670s 2242.239us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.960s 44.121us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.580s 25.686us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 10.890s 219.886us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 10.890s 219.886us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.450s 703.104us 1 1 100.00
alert_handler_csr_rw 5.850s 523.075us 1 1 100.00
alert_handler_csr_aliasing 156.150s 8696.601us 1 1 100.00
alert_handler_same_csr_outstanding 31.290s 713.327us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.450s 703.104us 1 1 100.00
alert_handler_csr_rw 5.850s 523.075us 1 1 100.00
alert_handler_csr_aliasing 156.150s 8696.601us 1 1 100.00
alert_handler_same_csr_outstanding 31.290s 713.327us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 105.030s 2920.459us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 105.030s 2920.459us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 105.030s 2920.459us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 105.030s 2920.459us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 732.500s 33053.269us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_tl_intg_err 15.220s 2069.768us 1 1 100.00
alert_handler_sec_cm 9.460s 934.078us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 15.220s 2069.768us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 105.030s 2920.459us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 2.290s 74.659us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 2.290s 74.659us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 2.290s 74.659us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 2.290s 74.659us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 8.200s 107.733us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 623.480s 12468.753us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 8.200s 107.733us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 437.880s 6814.559us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 437.880s 6814.559us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.460s 934.078us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.460s 934.078us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.460s 934.078us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.460s 934.078us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 9.460s 934.078us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.460s 934.078us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.460s 934.078us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.460s 934.078us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 9.460s 934.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 39.600s 1937.943us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (* [*] vs * [*])
alert_handler_ping_timeout 48208602634581566543101033600269903097605820313377432732222724334544257292016 78
UVM_ERROR @ 111144574 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 111144574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 45060213430021323415611517117292459999829107040926684334315565338335375789106 104
UVM_ERROR @ 1937943224 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1937943224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---