Simulation Results: chip

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.81 %
  • code
  • 84.89 %
  • assert
  • 96.44 %
  • func
  • 37.09 %
  • line
  • 94.08 %
  • branch
  • 92.85 %
  • cond
  • 89.04 %
  • toggle
  • 91.34 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
86.52%
V2S
100.00%
V3
63.33%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 142.050s 3262.067us 1 1 100.00
chip_sw_example_rom 72.770s 2195.477us 1 1 100.00
chip_sw_example_manufacturer 144.560s 2937.464us 1 1 100.00
chip_sw_example_concurrency 128.830s 2781.019us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 239.810s 7344.721us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 335.040s 5650.692us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 434.760s 6978.048us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3286.020s 27647.703us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
chip_csr_mem_rw_with_rand_reset 232.830s 6170.186us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3286.020s 27647.703us 1 1 100.00
chip_csr_rw 335.040s 5650.692us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 8.080s 217.450us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 274.810s 4780.075us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 274.810s 4780.075us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 274.810s 4780.075us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 326.210s 4317.510us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 326.210s 4317.510us 1 1 100.00
chip_sw_uart_tx_rx_idx1 372.830s 4299.940us 1 1 100.00
chip_sw_uart_tx_rx_idx2 342.350s 4689.020us 1 1 100.00
chip_sw_uart_tx_rx_idx3 387.770s 4137.344us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 916.920s 7216.838us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 920.850s 8256.460us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 632.500s 8281.778us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 170.340s 4871.741us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 170.340s 4871.741us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 168.750s 2999.009us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 290.950s 6918.122us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 193.530s 3273.464us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 429.460s 7516.606us 1 1 100.00
chip_tap_straps_testunlock0 489.900s 8197.419us 1 1 100.00
chip_tap_straps_rma 260.800s 4859.794us 1 1 100.00
chip_tap_straps_prod 886.640s 13205.553us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 120.380s 2496.606us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 664.550s 8643.927us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 370.230s 6289.518us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 370.230s 6289.518us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 591.120s 7590.757us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1033.520s 12776.820us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 360.950s 4326.900us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 530.270s 5970.440us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3320.470s 19039.699us 1 1 100.00
chip_sw_aes_enc_jitter_en 135.180s 3242.862us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 710.880s 6851.595us 1 1 100.00
chip_sw_hmac_enc_jitter_en 151.130s 3231.478us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1163.840s 9424.354us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 169.410s 3091.311us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 286.400s 4915.109us 1 1 100.00
chip_sw_clkmgr_jitter 116.870s 2939.932us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 167.380s 3069.226us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 454.980s 7364.447us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 237.000s 5036.032us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 160.190s 2985.071us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 237.000s 5036.032us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 103.010s 2724.520us 1 1 100.00
chip_sw_aes_smoketest 147.550s 3075.622us 1 1 100.00
chip_sw_aon_timer_smoketest 187.670s 3166.620us 1 1 100.00
chip_sw_clkmgr_smoketest 133.330s 3184.622us 1 1 100.00
chip_sw_csrng_smoketest 152.100s 2982.142us 1 1 100.00
chip_sw_entropy_src_smoketest 761.180s 6745.267us 1 1 100.00
chip_sw_gpio_smoketest 190.950s 3113.921us 1 1 100.00
chip_sw_hmac_smoketest 214.350s 3547.993us 1 1 100.00
chip_sw_kmac_smoketest 141.510s 2510.489us 1 1 100.00
chip_sw_otbn_smoketest 500.990s 5131.784us 1 1 100.00
chip_sw_pwrmgr_smoketest 189.970s 4826.455us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 282.110s 6489.335us 1 1 100.00
chip_sw_rv_plic_smoketest 137.890s 2485.693us 1 1 100.00
chip_sw_rv_timer_smoketest 173.100s 3308.828us 1 1 100.00
chip_sw_rstmgr_smoketest 150.230s 3088.033us 1 1 100.00
chip_sw_sram_ctrl_smoketest 91.230s 2892.602us 1 1 100.00
chip_sw_uart_smoketest 120.820s 2965.171us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 120.890s 2853.937us 1 1 100.00
chip_sw_rom_functests 1 1 100.00
rom_keymgr_functest 250.250s 4908.598us 1 1 100.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7652.150s 62375.761us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2342.140s 14852.891us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 146.480s 5294.277us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 140.120s 2626.973us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 222.910s 3290.040us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6710.810s 53261.929us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 6977.150s 56657.635us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 50.710s 2468.881us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 50.710s 2468.881us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3286.020s 27647.703us 1 1 100.00
chip_same_csr_outstanding 2905.330s 28723.650us 1 1 100.00
chip_csr_hw_reset 239.810s 7344.721us 1 1 100.00
chip_csr_rw 335.040s 5650.692us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3286.020s 27647.703us 1 1 100.00
chip_same_csr_outstanding 2905.330s 28723.650us 1 1 100.00
chip_csr_hw_reset 239.810s 7344.721us 1 1 100.00
chip_csr_rw 335.040s 5650.692us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 29.520s 1313.956us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.020s 40.438us 1 1 100.00
xbar_smoke_large_delays 50.470s 6918.007us 1 1 100.00
xbar_smoke_slow_rsp 55.450s 6178.081us 1 1 100.00
xbar_random_zero_delays 33.480s 463.170us 1 1 100.00
xbar_random_large_delays 244.910s 38574.747us 1 1 100.00
xbar_random_slow_rsp 132.830s 15499.241us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 21.350s 790.992us 1 1 100.00
xbar_error_and_unmapped_addr 17.200s 241.968us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 13.110s 233.658us 1 1 100.00
xbar_error_and_unmapped_addr 17.200s 241.968us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 36.150s 1346.105us 1 1 100.00
xbar_access_same_device_slow_rsp 110.570s 12394.896us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 26.330s 1463.683us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 178.880s 8621.519us 1 1 100.00
xbar_stress_all_with_error 205.420s 9814.858us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 33.440s 80.364us 1 1 100.00
xbar_stress_all_with_reset_error 75.990s 2707.609us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2342.140s 14852.891us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 2183.120s 28212.425us 0 1 0.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2477.170s 15716.368us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 1924.330s 10928.854us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2465.860s 15447.469us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2366.690s 16227.887us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2356.810s 15935.005us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2392.230s 15328.733us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 18.990s 10.300us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 19.790s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 16.710s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 26.650s 10.340us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 17.640s 10.380us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 27.700s 10.100us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 24.410s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 20.670s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 18.280s 10.340us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 16.000s 10.200us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.310s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 16.680s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 19.910s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 24.660s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 17.990s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 21.610s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 20.820s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 17.610s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 28.820s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 17.290s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18.170s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 17.200s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.770s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 16.490s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18.160s 10.340us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 1915.810s 12882.659us 1 1 100.00
rom_e2e_asm_init_dev 2407.400s 15355.537us 1 1 100.00
rom_e2e_asm_init_prod 2459.880s 16015.002us 1 1 100.00
rom_e2e_asm_init_prod_end 2275.620s 15525.305us 1 1 100.00
rom_e2e_asm_init_rma 2302.290s 19507.394us 1 1 100.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 2288.590s 15540.815us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 4214.110s 28777.581us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 2295.150s 18137.893us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2304.780s 16243.449us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2880.430s 34655.712us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2880.430s 34655.712us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 184.700s 3046.448us 1 1 100.00
chip_sw_aes_enc_jitter_en 135.180s 3242.862us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 142.370s 2931.720us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 129.510s 3182.569us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1387.610s 11095.950us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 189.970s 3431.251us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 292.230s 5622.745us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 410.190s 5424.262us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 532.510s 5320.606us 1 1 100.00
chip_plic_all_irqs_10 298.290s 3662.084us 1 1 100.00
chip_plic_all_irqs_20 337.100s 3884.714us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 181.290s 4016.666us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 974.510s 10194.494us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 394.110s 5942.764us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 134.470s 3056.258us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1028.740s 7868.100us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1101.170s 8855.468us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 797.130s 7751.524us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8281.380s 255807.701us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 205.540s 3472.188us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 189.970s 4826.455us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 205.540s 3472.188us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 456.360s 8377.582us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 456.360s 8377.582us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 266.460s 6627.827us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 298.510s 5460.124us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 513.610s 6399.635us 1 1 100.00
chip_sw_aes_idle 129.510s 3182.569us 1 1 100.00
chip_sw_hmac_enc_idle 175.090s 2789.999us 1 1 100.00
chip_sw_kmac_idle 106.570s 2557.369us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 268.900s 3469.702us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 239.390s 4429.754us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 267.510s 4343.293us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 267.320s 4531.578us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 732.040s 10668.096us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 328.220s 3677.725us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 357.270s 4804.140us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 371.600s 4287.909us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 397.030s 5023.751us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 343.750s 4178.157us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 321.070s 4456.777us 1 1 100.00
chip_sw_ast_clk_outputs 591.120s 7590.757us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 404.490s 8956.359us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 371.600s 4287.909us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 397.030s 5023.751us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 360.950s 4326.900us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 530.270s 5970.440us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3320.470s 19039.699us 1 1 100.00
chip_sw_aes_enc_jitter_en 135.180s 3242.862us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 710.880s 6851.595us 1 1 100.00
chip_sw_hmac_enc_jitter_en 151.130s 3231.478us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1163.840s 9424.354us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 169.410s 3091.311us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 286.400s 4915.109us 1 1 100.00
chip_sw_clkmgr_jitter 116.870s 2939.932us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 122.260s 2838.670us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 374.850s 3936.545us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 692.330s 7541.857us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 2879.580s 24965.592us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 157.040s 2821.734us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 145.030s 3396.240us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 494.500s 6732.269us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 194.000s 3292.618us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 285.440s 4649.509us 1 1 100.00
chip_sw_flash_init_reduced_freq 1060.820s 25622.806us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 1922.560s 17994.289us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 591.120s 7590.757us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 351.120s 4982.053us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 248.320s 3932.818us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 410.190s 5424.262us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1028.740s 7868.100us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 694.950s 6291.147us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 314.590s 5073.451us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 427.550s 7574.979us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 156.010s 3117.219us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 1973.340s 12548.722us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 155.100s 2653.975us 1 1 100.00
chip_sw_edn_entropy_reqs 673.030s 5837.302us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 155.100s 2653.975us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 694.950s 6291.147us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 115.620s 2615.096us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 951.400s 15544.213us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 518.540s 5443.713us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 530.270s 5970.440us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 317.210s 4118.684us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 360.950s 4326.900us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3370.180s 44770.564us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 951.400s 15544.213us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 243.600s 3382.797us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1169.000s 8857.294us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 325.260s 5189.859us 1 1 100.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3370.180s 44770.564us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 325.260s 5189.859us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 325.260s 5189.859us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_wr_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 325.260s 5189.859us 1 1 100.00
chip_sw_flash_lc_seed_hw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 325.260s 5189.859us 1 1 100.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 410.190s 5424.262us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 161.870s 8502.163us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 546.880s 4960.136us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 352.410s 4535.995us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 352.410s 4535.995us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 137.170s 3076.621us 1 1 100.00
chip_sw_hmac_enc_jitter_en 151.130s 3231.478us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 175.090s 2789.999us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1237.740s 10117.553us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 741.030s 5567.075us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 363.770s 5300.132us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 353.390s 4949.876us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 453.150s 5831.915us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 266.880s 3500.988us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1169.000s 8857.294us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1163.840s 9424.354us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 983.810s 7926.570us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1387.610s 11095.950us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2059.920s 11393.897us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 158.260s 3245.414us 1 1 100.00
chip_sw_kmac_mode_kmac 188.930s 3545.868us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 169.410s 3091.311us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1169.000s 8857.294us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 556.580s 9396.931us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 101.220s 2776.318us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1372.570s 10687.142us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 106.570s 2557.369us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 292.230s 5622.745us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 429.460s 7516.606us 1 1 100.00
chip_tap_straps_rma 260.800s 4859.794us 1 1 100.00
chip_tap_straps_prod 886.640s 13205.553us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 142.030s 2799.357us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 556.580s 9396.931us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 556.580s 9396.931us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 556.580s 9396.931us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 775.140s 7666.224us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_prim_tl_access 161.870s 8502.163us 1 1 100.00
chip_rv_dm_lc_disabled 34.050s 2162.651us 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 325.260s 5189.859us 1 1 100.00
chip_sw_flash_rma_unlocked 3370.180s 44770.564us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 175.190s 2993.848us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 549.480s 6739.438us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 592.170s 6218.328us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 446.850s 7434.441us 0 1 0.00
chip_sw_lc_ctrl_transition 556.580s 9396.931us 1 1 100.00
chip_sw_keymgr_key_derivation 1169.000s 8857.294us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 365.500s 8998.953us 1 1 100.00
chip_sw_sram_ctrl_execution_main 357.160s 6376.806us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 404.490s 8956.359us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 328.220s 3677.725us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 357.270s 4804.140us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 371.600s 4287.909us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 397.030s 5023.751us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 343.750s 4178.157us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 321.070s 4456.777us 1 1 100.00
chip_tap_straps_dev 429.460s 7516.606us 1 1 100.00
chip_tap_straps_rma 260.800s 4859.794us 1 1 100.00
chip_tap_straps_prod 886.640s 13205.553us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 154.920s 2969.955us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 105.570s 3812.259us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 107.690s 3417.503us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 87.370s 2861.414us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_rv_dm_lc_disabled 34.050s 2162.651us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1391.750s 22691.570us 1 1 100.00
chip_sw_lc_walkthrough 5 5 100.00
chip_sw_lc_walkthrough_dev 3645.630s 49025.185us 1 1 100.00
chip_sw_lc_walkthrough_prod 3904.570s 47556.457us 1 1 100.00
chip_sw_lc_walkthrough_prodend 474.350s 7517.111us 1 1 100.00
chip_sw_lc_walkthrough_rma 3464.250s 45556.320us 1 1 100.00
chip_sw_lc_walkthrough_testunlocks 1391.750s 22691.570us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 69.940s 2871.198us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 64.270s 2437.038us 1 1 100.00
rom_volatile_raw_unlock 55.020s 2392.456us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3255.150s 17388.875us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3320.470s 19039.699us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 513.610s 6399.635us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 513.610s 6399.635us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 513.610s 6399.635us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 250.860s 3667.925us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 556.580s 9396.931us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 951.400s 15544.213us 1 1 100.00
chip_sw_otbn_mem_scramble 250.860s 3667.925us 1 1 100.00
chip_sw_keymgr_key_derivation 1169.000s 8857.294us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 287.550s 5051.162us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 95.750s 2586.500us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 951.400s 15544.213us 1 1 100.00
chip_sw_otbn_mem_scramble 250.860s 3667.925us 1 1 100.00
chip_sw_keymgr_key_derivation 1169.000s 8857.294us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 287.550s 5051.162us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 95.750s 2586.500us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 556.580s 9396.931us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 294.700s 4701.153us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 142.030s 2799.357us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 161.870s 8502.163us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 175.190s 2993.848us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 549.480s 6739.438us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 592.170s 6218.328us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 446.850s 7434.441us 0 1 0.00
chip_sw_lc_ctrl_transition 556.580s 9396.931us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 161.870s 8502.163us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 803.140s 7352.999us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 321.530s 8414.417us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 922.270s 25769.168us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 293.490s 7446.910us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 261.330s 7611.759us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 321.770s 7372.006us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 921.910s 23911.200us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 169.750s 5026.707us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 456.360s 8377.582us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 639.520s 9641.308us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 272.310s 3858.867us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 321.530s 8414.417us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 171.680s 3375.840us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 478.700s 8107.179us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 317.960s 8379.606us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 297.970s 4876.287us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1219.560s 20691.735us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 680.280s 7978.908us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 755.310s 12057.618us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1275.150s 23754.534us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 153.810s 3331.396us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 410.190s 5424.262us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 365.500s 8998.953us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 365.500s 8998.953us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 755.310s 12057.618us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1219.560s 20691.735us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 272.310s 3858.867us 1 1 100.00
chip_sw_pwrmgr_smoketest 189.970s 4826.455us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 249.110s 4704.157us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 261.440s 4364.581us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 265.780s 3830.947us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 974.510s 10194.494us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 138.800s 3348.029us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 410.190s 5424.262us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1101.170s 8855.468us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 448.390s 4638.054us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 467.720s 4912.928us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 151.780s 3117.896us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 95.750s 2586.500us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 261.440s 4364.581us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 261.440s 4364.581us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1273.750s 20560.098us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 960.030s 13106.473us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 249.110s 4704.157us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 132.460s 3259.273us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 294.620s 6151.078us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 260.800s 4859.794us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 34.050s 2162.651us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 532.510s 5320.606us 1 1 100.00
chip_plic_all_irqs_10 298.290s 3662.084us 1 1 100.00
chip_plic_all_irqs_20 337.100s 3884.714us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 164.350s 2817.538us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 145.740s 2661.215us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2342.140s 14852.891us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 477.640s 8091.390us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 216.490s 3861.858us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 191.370s 3725.207us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 158.160s 2297.099us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 287.550s 5051.162us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 286.400s 4915.109us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 437.790s 8511.381us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 380.450s 8659.542us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 357.160s 6376.806us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 410.190s 5424.262us 1 1 100.00
chip_sw_data_integrity_escalation 370.230s 6289.518us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 680.280s 7978.908us 1 1 100.00
chip_sw_sysrst_ctrl_reset 972.360s 22827.884us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 178.510s 3651.331us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 233.510s 4456.736us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 290.630s 4407.142us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 972.360s 22827.884us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 972.360s 22827.884us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 692.140s 10823.622us 0 1 0.00
chip_sw_sysrst_ctrl_flash_wp_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 692.140s 10823.622us 0 1 0.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 346.380s 6161.781us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2880.430s 34655.712us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 166.330s 2969.542us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 122.320s 3035.567us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 262.200s 3892.755us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 302.000s 4269.592us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1101.720s 8399.655us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4741.900s 31762.426us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1850.490s 11594.710us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 122.230s 3033.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 168.040s 2352.872us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 136.680s 2968.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 8908.440s 72294.105us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 962.570s 6814.307us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 401.450s 4968.654us 0 1 0.00
rom_e2e_jtag_debug_dev 187.970s 3593.709us 0 1 0.00
rom_e2e_jtag_debug_rma 169.020s 4552.114us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 59.720s 1942.812us 0 1 0.00
rom_e2e_jtag_inject_dev 61.270s 2860.058us 0 1 0.00
rom_e2e_jtag_inject_rma 91.470s 2877.636us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 8.742s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 1 1 100.00
chip_sw_clkmgr_jitter_frequency 514.700s 4865.528us 1 1 100.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 273.490s 2767.655us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 656.590s 4769.159us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1119.590s 8956.025us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 231.680s 2000.035us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 526.490s 5120.325us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 54.750s 2190.373us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 159.250s 3616.461us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 273.150s 5061.321us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 236.760s 4427.903us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 755.310s 12057.618us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 401.450s 4968.654us 0 1 0.00
rom_e2e_jtag_debug_dev 187.970s 3593.709us 0 1 0.00
rom_e2e_jtag_debug_rma 169.020s 4552.114us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 328.630s 4548.110us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 410.190s 5424.262us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5229.590s 38168.323us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5229.590s 38168.323us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 160.800s 3739.109us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 326.210s 4317.510us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2982.010s 19175.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 154.500s 3293.263us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 324.520s 4318.301us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 70.540s 2261.366us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 116.270s 2619.877us 1 1 100.00
chip_sw_otp_ctrl_descrambling 208.920s 2623.992us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 215.730s 3946.116us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.133s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 231.330s 3425.014us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37451) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 113439739546402978304726159265277831431565224903730596632270869211313671161335 214
UVM_ERROR @ 2468.880925 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37451) { a_addr: 'h10734 a_data: 'hca899a40 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h1a95e d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2468.880925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 47845366410789790646517902412548507311223017563010373227757997746534304689184 212
UVM_ERROR @ 2162.651498 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10368 read out mismatch
UVM_INFO @ 2162.651498 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]
chip_sw_sleep_pin_mio_dio_val 40834516055309218124045476836489874166542485951435195293455626437719244571906 563
UVM_ERROR @ 2999.009000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
UVM_INFO @ 2999.009000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch
chip_sw_spi_device_pass_through_collision 63146806887922386687738576567233460764748118586949331592127884046367703518743 404
UVM_ERROR @ 3861.857501 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 91355941617596123138425419800322871799022486631838851269702296046540862314954 426
UVM_ERROR @ 7434.441264 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7434.441264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 35741828662396824751633685432960077510343155221800915656665690996594238089758 402
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3616.460724 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3616.460724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
chip_sw_otp_ctrl_rot_auth_config 58375480921581699545716197148372993952138086951151485130876854962361314329638 416
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 27828233233203509513542422113918284072819586450845116038331224168679343714419 409
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 98314317409761331417882556035797167755795831451016288512140933259271641796743 496
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 57503956922672962659586805672582282095132577050060839119792146730172859091621 461
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 9289669198024449958949726194015276384495111108037759685592800820033764695812 429
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 6304890934344044030580778349260007993196566546237799335574208328820456490895 462
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 73868566496497495977290207079130629077138987885285509851085377824251282983907 440
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 42740551072286910761634657176845342649255115687496898237482638286185521852590 423
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@102429) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 91369375363682497727477607339945570150462091487369357559269507603984513300145 415
UVM_ERROR @ 4364.581140 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@102429) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4364.581140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 70516534990747645939387273001319890813741768668930561053295292729006507484089 409
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 5026.706500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5026.706500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 113604422556031118151345814272088279234972843224182216280756927184660404953658 408
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7611.759000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7611.759000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 92997412839480453631460336147106847494028243896603277528859402112825813374605 410
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 8107.179000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8107.179000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
chip_sw_sysrst_ctrl_ec_rst_l 26961962241160932606797768775670264579217180746862521739212756816985129156981 401
UVM_ERROR @ 10823.622064 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
UVM_INFO @ 10823.622064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 83563452441684822687170669622528538369995394833154834168684636516542006984406 413
UVM_ERROR @ 34655.711643 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34655.711643 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 213933101915382541832111692305715156983324937406826926859314776137765122392 390
UVM_ERROR @ 3431.250715 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
UVM_INFO @ 3431.250715 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 55793285034914345880497698141844458994806806345518144155624943952319431007577 391
UVM_ERROR @ 3056.258190 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3056.258190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 77187549798095629847143006149145454809818198728154404420161899967230933539569 None
Job timed out after 240 minutes
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 93182323631387477452019030739630025587711934478122886858719451286954642298565 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.179s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 66001610495575608208539350408294824939951622215615470750822599254234612861866 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.146s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 72682111013174656948526797752045034629826531545032220644087433951789614777562 402
UVM_ERROR @ 2626.973000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 2626.973000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 70534444815678973052073375475633508356432171384916181088049848353164214541001 401
UVM_ERROR @ 3290.040000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3290.040000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
chip_sw_ast_clk_rst_inputs 38849394764552027631370915827767941612100816950367436134526354203356911022824 414
UVM_ERROR @ 12776.819865 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 12776.819865 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'
rom_e2e_shutdown_output 67166518227780350717328539802202514201341457837017567272807905981723177364976 466
Offending '(pend_req[h2d.a_source].pend == 0)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 23953649300ps failed at 23953649300ps
Offending '(pend_req[h2d.a_source].pend == 0)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 23953850452ps failed at 23953850452ps
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 85948776448759961266986062913227035665399379364332651675443851847916911660378 504
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 84781687857747152498156001233507135182273980459900253389990139144431825988981 501
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 37599116042204916951512063401474711065960218440680869020326069539697702751481 472
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 21055482433106850563214993351022177635559613334612824097703880469671121302700 471
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 77144852853083421086775210063285496737624206949642624219548747849141010825626 497
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 78323373762529319903484566565537466068655346388717760490707087886643285396153 477
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 26690171998768726482660612316513846443925298591194889398171159052733172944176 502
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 78144679287156109548112137164982782824919596802440526994656668648608845108771 472
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 7043420677192253326559995801064374195916519480082878557490659825817259596333 504
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 85107942739487315633422489024778559692610930075092040025805219768721333921554 513
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 81467433368931345283384949717273976983740299405299754545494786958372153284277 601
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 69958320368187579004685979139467047690233943264315461170768829756092274287892 624
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 59655285071045600441230727053462858178937992932992226456676035972594712833641 619
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 61029436047068350659704838726714952611890494919019549327336875626506926788083 500
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 45988404730391463317463658001741310302984197761439289715522227083726685346911 504
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 110170234452606292811858822692030156126741100271000971254257397585176103490526 472
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 109283431538925913555854846344960798364587191248703048825324587068607966646889 546
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 59893065377261427866075518761985074441336493963508997503418483437796762831483 500
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 77806062593979783919533611540526842984367585576412748705365342100830292052604 576
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 110086000165363325072567894059175348244821382607204454317193626599993365580882 506
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 89244493014639361237829606433589875403258203191933030575017191049030105833912 498
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 12855747938617054916180599874301878422310780824726754193050889868768268045295 466
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 48455153023773622500626046516513399545899379767895867450218733865860483296121 474
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 6106605679314236907230139938711944156049719325061969851901502778025468617738 486
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 92773264767291039936686359139768681534432112768081881501871008710629375283813 520
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 51154789711868454531375821450743748047576570303516937589665367626501885485967 413
UVM_ERROR @ 15540.815198 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 15540.815198 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 37042997309443603749155468836769609686487172516477575722297823076457041055157 425
UVM_ERROR @ 18137.893226 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 18137.893226 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---