Simulation Results: clkmgr

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.13 %
  • code
  • 98.62 %
  • assert
  • 96.47 %
  • func
  • 87.31 %
  • line
  • 99.22 %
  • branch
  • 98.91 %
  • cond
  • 94.96 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.770s 18.509us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.830s 73.186us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.840s 136.702us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.570s 397.819us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.890s 21.957us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.130s 93.280us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.840s 136.702us 1 1 100.00
clkmgr_csr_aliasing 0.890s 21.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.650s 34.451us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.670s 18.991us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.730s 25.253us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.690s 24.016us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.770s 18.509us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 5.940s 2400.775us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.600s 1216.850us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 5.940s 2400.775us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 0.960s 116.121us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.700s 23.279us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.790s 84.740us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.790s 84.740us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.830s 73.186us 1 1 100.00
clkmgr_csr_rw 0.840s 136.702us 1 1 100.00
clkmgr_csr_aliasing 0.890s 21.957us 1 1 100.00
clkmgr_same_csr_outstanding 2.030s 740.539us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.830s 73.186us 1 1 100.00
clkmgr_csr_rw 0.840s 136.702us 1 1 100.00
clkmgr_csr_aliasing 0.890s 21.957us 1 1 100.00
clkmgr_same_csr_outstanding 2.030s 740.539us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 1.730s 354.473us 1 1 100.00
clkmgr_tl_intg_err 1.840s 194.332us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.840s 233.874us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.840s 233.874us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.840s 233.874us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.840s 233.874us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.690s 334.336us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.840s 194.332us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 5.940s 2400.775us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.600s 1216.850us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.840s 233.874us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.570s 471.507us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.660s 15.817us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.190s 302.809us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.840s 104.345us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.420s 403.528us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.840s 136.702us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 1.730s 354.473us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.840s 136.702us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.840s 136.702us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 1.730s 354.473us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.140s 1322.386us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 55.250s 9721.219us 1 1 100.00

Error Messages

   Test seed line log context