| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
Traceback (most recent call last):
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 88, in <module>
main()
~~~~^^
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 32, in main
gapi = yaml.load(open(gapi_filepath), Loader=YamlLoader)
~~~~^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: '/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d/ral_input.yml'
ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d"
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| cover_reg_top | None | None |
os.makedirs(work_root)
~~~~~~~~~~~^^^^^^^^^^^
File "<frozen os>", line 227, in makedirs
FileExistsError: [Errno 17] File exists: '/nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work'
INFO: Mapped lowrisc:prim:ram_1p:0 to lowrisc:prim_generic:ram_1p:0.
INFO: Mapped lowrisc:prim:clock_buf:0 to lowrisc:prim_generic:clock_buf:0.
INFO: Mapped lowrisc:prim:clock_gating:0 to lowrisc:prim_generic:clock_gating:0.
INFO: Mapped lowrisc:prim:clock_inv:0 to lowrisc:prim_generic:clock_inv:0.
INFO: Mapped lowrisc:prim:rst_sync:0 to lowrisc:prim_generic:rst_sync:0.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_tl_errors | 14645343330808056403458182796688761004066311295716214450546039659545473061650 | None | ||
| edn_tl_intg_err | 68327857630264975632069079862945395624737923513990542248009057276577192069852 | None | ||
| edn_intr_test | 61211533502746109865745007621183289192768328302152098030390961272628519049976 | None | ||
| edn_csr_hw_reset | 75020109202504968490895170557726618882435825726839724803084535467129370099872 | None | ||
| edn_csr_rw | 76851125363365204726081634025448590898227799059566974076160087207667113330771 | None | ||
| edn_csr_bit_bash | 58201002766703521594674769174902412849352346736174731405461256705398702142614 | None | ||
| edn_csr_aliasing | 2587427823823091831422059457461318948016733394763731965150090895299634725341 | None | ||
| edn_same_csr_outstanding | 47359293891718093710543341770708674421077142852989456445500890639780631167970 | None | ||
| edn_csr_mem_rw_with_rand_reset | 29973657588591715074277189882230505816961093876412464853500378766300004551980 | None | ||
| edn_smoke | 33584279310248936385970539673111737930265920363734152577873805499126514038365 | None | ||
| edn_regwen | 106910378544645167182878734253590936516404409565171845180924758698071866150483 | None | ||
| edn_genbits | 39077326360781301544723089610677546049140192798154444983174026821114005954923 | None | ||
| edn_stress_all | 104488843496353447045218404882443870831225916411066340680231290203757496834858 | None | ||
| edn_stress_all_with_rand_reset | 66000872395578796699537670685924323703340539266556345297851977199189383114155 | None | ||
| edn_intr | 54042483187903121816735445878665028682212840457503647852480373723439281085547 | None | ||
| edn_alert | 58074408105575201706563689921687258465348366224401251105273641723279245940030 | None | ||
| edn_err | 29182021533090969806115859483110971418068543410710507262970484889994040503535 | None | ||
| edn_disable | 64969533951404692892174660163979071606489626438745422604710533811464413609812 | None | ||
| edn_disable_auto_req_mode | 53026307776466013700311088394060169247277330307981068769695292641270018965996 | None | ||
| edn_sec_cm | 12478945359949620030783763106255508457304615651877643297037590542218704716348 | None | ||
| edn_alert_test | 70339321345408776598322135115347047417142589528524031344071457723727423069023 | None | ||
| edn | None | None | ||
| edn | None | None | ||