| V1 |
|
87.50% |
| V2 |
|
52.38% |
| V2S |
|
16.67% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| edn_csr_hw_reset | 0.700s | 69.178us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| edn_csr_rw | 0.710s | 75.509us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| edn_csr_bit_bash | 2.120s | 115.551us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| edn_csr_aliasing | 0.860s | 23.488us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| edn_csr_mem_rw_with_rand_reset | 1.000s | 112.034us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| edn_csr_rw | 0.710s | 75.509us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 0.860s | 23.488us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| edn_intr_test | 0.750s | 20.867us | 1 | 1 | 100.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| edn_tl_errors | 2.100s | 181.036us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| edn_tl_errors | 2.100s | 181.036us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| edn_csr_hw_reset | 0.700s | 69.178us | 1 | 1 | 100.00 | |
| edn_csr_rw | 0.710s | 75.509us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 0.860s | 23.488us | 1 | 1 | 100.00 | |
| edn_same_csr_outstanding | 1.110s | 261.589us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| edn_csr_hw_reset | 0.700s | 69.178us | 1 | 1 | 100.00 | |
| edn_csr_rw | 0.710s | 75.509us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 0.860s | 23.488us | 1 | 1 | 100.00 | |
| edn_same_csr_outstanding | 1.110s | 261.589us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_tl_intg_err | 1.370s | 68.628us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| edn_tl_intg_err | 1.370s | 68.628us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 88, in <module>
main()
~~~~^^
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 32, in main
gapi = yaml.load(open(gapi_filepath), Loader=YamlLoader)
~~~~^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: '/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d/ral_input.yml'
ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d"
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_smoke | 81732516754986743363330868209722676576992546611819204410161901563622889188830 | None | ||
| edn_regwen | 23098737377997276982511631580612156167038960709181379497308023396445381635768 | None | ||
| edn_genbits | 86229274690968584762609050881565188842015089464472761221761506506148614888523 | None | ||
| edn_stress_all | 72040652647039348218318183225845230351477819388599684649367526788760202520765 | None | ||
| edn_stress_all_with_rand_reset | 64364211654279502456581632851187779498072105005350147355383454987710756007932 | None | ||
| edn_intr | 80345951815144973993683491749012044588687522623653536157241138038177949456279 | None | ||
| edn_alert | 54372701971637145829333872368267078652633312275352603490208022584131729820738 | None | ||
| edn_err | 37551900429571050155991416657010394114012741131886976535759823088327967781433 | None | ||
| edn_disable | 41606874929346527811276038786245291949604219805842490026773889163557826061193 | None | ||
| edn_disable_auto_req_mode | 53520782444712664868660974484412494497180578521389364816746230686733967629201 | None | ||
| edn_sec_cm | 60848048767510040194157883536155664284099767106914341757465105186119985770850 | None | ||
| edn_alert_test | 114163138722453176113287910182351691603203241893299701037860023596785035322041 | None | ||