Simulation Results: flash_ctrl

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.33 %
  • code
  • 93.83 %
  • assert
  • 96.62 %
  • func
  • 95.54 %
  • line
  • 95.91 %
  • branch
  • 97.08 %
  • cond
  • 93.17 %
  • toggle
  • 97.94 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.73%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 88.760s 70.455us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.240s 58.226us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 19.160s 27.867us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 5.740s 21.680us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 31.900s 4944.183us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 30.190s 2713.802us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 14.390s 209.419us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 5.740s 21.680us 1 1 100.00
flash_ctrl_csr_aliasing 30.190s 2713.802us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.390s 29.253us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.460s 41.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.090s 24.680us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 20.120s 71.222us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1180.240s 87496.529us 1 1 100.00
flash_ctrl_hw_rma_reset 573.630s 160194.639us 1 1 100.00
flash_ctrl_lcmgr_intg 6.000s 23.690us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1515.040s 522067.256us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 128.870s 3081.086us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.100s 33.492us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1828.530s 123709.175us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 35.890s 193.468us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 24.610s 63.315us 1 1 100.00
flash_ctrl_rw_evict_all_en 22.240s 98.010us 1 1 100.00
flash_ctrl_re_evict 17.440s 114.525us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 107.280s 95.183us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 107.280s 95.183us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 161.730s 11186.211us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 11.490s 102.950us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 77.420s 102.526us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 334.580s 40418.196us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 267.640s 629.896us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1217.570s 9637.122us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.840s 40.842us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 105.380s 1144.222us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.450s 50.197us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.660s 52.630us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 17.190s 286.172us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 65.410s 9848.817us 1 1 100.00
flash_ctrl_otp_reset 55.590s 79.599us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1180.240s 87496.529us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 124.300s 3825.276us 1 1 100.00
flash_ctrl_intr_wr 53.590s 11748.677us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 77.850s 11406.167us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 130.150s 23443.058us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 44.010s 1821.993us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 33.430s 1295.283us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.900s 83.228us 1 1 100.00
flash_ctrl_ro_derr 88.740s 648.337us 1 1 100.00
flash_ctrl_rw_derr 138.050s 1526.830us 1 1 100.00
flash_ctrl_derr_detect 103.790s 871.819us 1 1 100.00
flash_ctrl_integrity 388.760s 3565.367us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 9.660s 23.949us 1 1 100.00
flash_ctrl_ro_serr 83.630s 574.694us 1 1 100.00
flash_ctrl_rw_serr 147.380s 3976.294us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 36.320s 7392.375us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 61.540s 1982.305us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 155.150s 9887.761us 1 1 100.00
flash_ctrl_write_word_sweep 7.090s 43.517us 1 1 100.00
flash_ctrl_read_word_sweep 9.300s 26.394us 1 1 100.00
flash_ctrl_ro 85.930s 2842.882us 1 1 100.00
flash_ctrl_rw 447.480s 51221.315us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 23.700s 327.887us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 649.190s 81493.966us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 39.640s 10084.902us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.570s 77.710us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 8.960s 57.203us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 10.170s 35.257us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 10.170s 35.257us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 19.160s 27.867us 1 1 100.00
flash_ctrl_csr_rw 5.740s 21.680us 1 1 100.00
flash_ctrl_csr_aliasing 30.190s 2713.802us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.810s 79.838us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 19.160s 27.867us 1 1 100.00
flash_ctrl_csr_rw 5.740s 21.680us 1 1 100.00
flash_ctrl_csr_aliasing 30.190s 2713.802us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.810s 79.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 9.450s 102.058us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 9.450s 102.058us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 9.450s 102.058us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 9.450s 102.058us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 24.400s 265.894us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 340.910s 336.606us 1 1 100.00
flash_ctrl_sec_cm 1522.350s 2635.223us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 340.910s 336.606us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 340.910s 336.606us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.150s 284.713us 1 1 100.00
flash_ctrl_wr_intg 6.670s 71.710us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 88.760s 70.455us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 55.590s 79.599us 1 1 100.00
flash_ctrl_disable 9.450s 50.197us 1 1 100.00
flash_ctrl_sec_info_access 46.150s 2366.166us 1 1 100.00
flash_ctrl_connect 7.660s 52.630us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 7.540s 201.936us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.740s 21.680us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.450s 102.058us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.740s 21.680us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.450s 102.058us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.740s 21.680us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.450s 102.058us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.450s 50.197us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.150s 284.713us 1 1 100.00
flash_ctrl_access_after_disable 6.500s 38.344us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 10.910s 95.453us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.450s 50.197us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 11.490s 102.950us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 447.480s 51221.315us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 147.380s 3976.294us 1 1 100.00
flash_ctrl_rw_derr 138.050s 1526.830us 1 1 100.00
flash_ctrl_integrity 388.760s 3565.367us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1180.240s 87496.529us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1522.350s 2635.223us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1522.350s 2635.223us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1522.350s 2635.223us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1522.350s 2635.223us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.280s 750.725us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 6.180s 29.696us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.110s 38.617us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1522.350s 2635.223us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1522.350s 2635.223us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1522.350s 2635.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 18.930s 107.127us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 357.510s 1543.353us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
flash_ctrl_phy_host_grant_err 31367786886126769345263914795562555302347015047700808129212782122275695019975 122
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
UVM_ERROR @ 29695.8 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 29695.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---