Simulation Results: hmac

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.13 %
  • code
  • 97.43 %
  • assert
  • 96.42 %
  • func
  • 43.53 %
  • line
  • 99.79 %
  • branch
  • 99.67 %
  • cond
  • 96.51 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 5.330s 582.009us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.760s 188.763us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.830s 112.976us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.380s 1578.609us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.050s 732.220us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.150s 51.227us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.830s 112.976us 1 1 100.00
hmac_csr_aliasing 4.050s 732.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 50.670s 6237.370us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 32.300s 2779.278us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.560s 750.776us 1 1 100.00
hmac_test_sha384_vectors 361.980s 16911.360us 1 1 100.00
hmac_test_sha512_vectors 18.510s 260.076us 1 1 100.00
hmac_test_hmac256_vectors 6.210s 412.532us 1 1 100.00
hmac_test_hmac384_vectors 6.450s 210.597us 1 1 100.00
hmac_test_hmac512_vectors 6.450s 188.353us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 22.550s 2905.961us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 308.560s 9460.530us 1 1 100.00
error 1 1 100.00
hmac_error 60.990s 1622.466us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 16.530s 874.307us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 5.330s 582.009us 1 1 100.00
hmac_long_msg 50.670s 6237.370us 1 1 100.00
hmac_back_pressure 32.300s 2779.278us 1 1 100.00
hmac_datapath_stress 308.560s 9460.530us 1 1 100.00
hmac_burst_wr 22.550s 2905.961us 1 1 100.00
hmac_stress_all 32.000s 12845.601us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 5.330s 582.009us 1 1 100.00
hmac_long_msg 50.670s 6237.370us 1 1 100.00
hmac_back_pressure 32.300s 2779.278us 1 1 100.00
hmac_datapath_stress 308.560s 9460.530us 1 1 100.00
hmac_wipe_secret 16.530s 874.307us 1 1 100.00
hmac_test_sha256_vectors 7.560s 750.776us 1 1 100.00
hmac_test_sha384_vectors 361.980s 16911.360us 1 1 100.00
hmac_test_sha512_vectors 18.510s 260.076us 1 1 100.00
hmac_test_hmac256_vectors 6.210s 412.532us 1 1 100.00
hmac_test_hmac384_vectors 6.450s 210.597us 1 1 100.00
hmac_test_hmac512_vectors 6.450s 188.353us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 5.330s 582.009us 1 1 100.00
hmac_long_msg 50.670s 6237.370us 1 1 100.00
hmac_back_pressure 32.300s 2779.278us 1 1 100.00
hmac_datapath_stress 308.560s 9460.530us 1 1 100.00
hmac_burst_wr 22.550s 2905.961us 1 1 100.00
hmac_error 60.990s 1622.466us 1 1 100.00
hmac_wipe_secret 16.530s 874.307us 1 1 100.00
hmac_test_sha256_vectors 7.560s 750.776us 1 1 100.00
hmac_test_sha384_vectors 361.980s 16911.360us 1 1 100.00
hmac_test_sha512_vectors 18.510s 260.076us 1 1 100.00
hmac_test_hmac256_vectors 6.210s 412.532us 1 1 100.00
hmac_test_hmac384_vectors 6.450s 210.597us 1 1 100.00
hmac_test_hmac512_vectors 6.450s 188.353us 1 1 100.00
hmac_stress_all 32.000s 12845.601us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 32.000s 12845.601us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.570s 24.338us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.610s 19.678us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.530s 152.754us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.530s 152.754us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.760s 188.763us 1 1 100.00
hmac_csr_rw 0.830s 112.976us 1 1 100.00
hmac_csr_aliasing 4.050s 732.220us 1 1 100.00
hmac_same_csr_outstanding 1.710s 209.335us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.760s 188.763us 1 1 100.00
hmac_csr_rw 0.830s 112.976us 1 1 100.00
hmac_csr_aliasing 4.050s 732.220us 1 1 100.00
hmac_same_csr_outstanding 1.710s 209.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.910s 181.422us 1 1 100.00
hmac_tl_intg_err 2.960s 281.489us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.960s 281.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 5.330s 582.009us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.830s 253.405us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 28.300s 2083.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.840s 24.947us 1 1 100.00

Error Messages

   Test seed line log context